• Proceedings of the Korea Society for Simulation Conference
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• 1997.04a
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• pp.36-38
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• 1997

본 논문은 gate-level timed circuits의 자동 합성과 검증에 대한 것으로, 동기 회 로는 디자인을 최적화하기 위해 합성 절차가 사용된 동안 설계서에 명시된 시간 정보에 속 한 비동기 회로의 일부로서 이 시스템은 열거된 일반적인 회로 작용과 시간의 요구 조건에 대해 설계를 해석한다. 이 설계는 영향을 미치는 상태 공간을 구하기 위해 정확하고 효과적 인 시간 해석 알고리즘을 사용해 해석할 수 있는 그래픽 표현으로 자동적으로 변환된다. 이 상태공간으로부터 합성 절차는 standard-cells과 gate-arrays와 같은 반 주문형 반도체로 매핑을 용이하게 하기 위해 기본 게이트만을 사용해 어려움을 해결하는 시간에 대한 회로 유도된다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.379-383
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• 2003

The subthreshold characteristics of Double-Gate MOSFETs are analyzed for various Tsi. In the lightly-doped asymmetric device, it is found that the subthreshold current dramatically increases as the Tsi increases and this phenomenon is due to the linear distribution of potential in the channel region with low depletion-charge. Further, we derived an analytical equation which can explain this phenomenon and verified the accuracy of analytical equation by comparing with the result of device simulation.

• Magazine of the Korean Society of Agricultural Engineers
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• v.45 no.1
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• pp.91-101
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• 2003

Boryeong Seadike located at southwestern seashore of Korean peninsula completed in 1997. Sluice gate operation can be an important factor to maintain lake water quality and reduce retaining time of pollutants within lake. The lake water quality simulation model, WASPS was adopted and tested to find out proper gate operation timing and discharge amount. From the simulation of sluice gate operation, the results showed that the later the time of discharge for loosing 1 day successively to 6 days, the better the quality of water. Discharge amount showed relatively minor changes of water quality. This means that pollutants flowed into lake from watershed do not have enough time to mix up with deep water when the gate opened at early time. About 3 days delay of discharge caused the dilution effect to stabilize the lake water quality in case of Boryeong freshwater lake.

• Transactions on Electrical and Electronic Materials
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• v.16 no.3
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• pp.156-161
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• 2015

In this paper, we present simulation results obtained using SILVACO TCAD tools for a 3-D silicon on insulator (SOI) n-FinFET structure with a gate length of 8 nm at 300K. The effects of variations of the device’s key electrical parameters, such as threshold voltage, subthreshold slope, transconductance, drain induced barrier lowering, oncurrent, leakage current and on/off current ratio are presented and analyzed. We will also describe some simulation results related to the influence of the gate work function variations on the considered structure. These variations have a direct impact on the electrical device characteristics. The results show that the threshold voltage decreases when we reduce the gate metal work function Φ_m. As a consequence, the behavior of the leakage current improves with increased Φ_m. Therefore, the short channel effects in real 3-D FinFET structures can reasonably be controlled and improved by proper adjustment of the gate metal work function.

• Korea Science and Art Forum
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• v.20
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• pp.421-428
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• 2015

Electronic/hybrid car and electroplating rectifier should have switching devices such as SCR, MOSFET, IGBT. And those switching devices should be operated by gate driver. In this paper, we propose high power gate driver that contains H-Bridge using 4 BJTs. H-Bridge and transformer generate isolate power. And gate control signal is transferred to isolated one by photo coupler and operate real switching device. We designed H-Bridge and 555-Timer by PSpice simulation and manufactured real product. Finally we succeed to operate 27V 50,000A electroplating rectifier using proposed gate driver.

• Progress in Superconductivity and Cryogenics
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• v.5 no.1
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• pp.44-47
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• 2003

There are several simulation programs in studying superconductor RSFQ (Rapid Single flux Quantum) electronic devices, which include WRspice, WinS, PSCAN, and JSIM. Even though different research groups use different simulation programs, it is not well known about which program gives the simulation results closer to the measurement values. In this work, we used both WRspice and WinS to simulate RSFQ OR gate and to compare the results from the different simulations. This comparison would help in deciding which program is better in the RSFQ circuit design. In the confluence buffer, which is the one of the main components of the DR gate, the measured bias margins were ${\times}23.2%$, while the margins from the simulations were ${\pm}35.56%$ from WRspice and it 53.1% from WinS. However, with the actual fabricated circuit parameters WRspice gave ${\pm}27%$. In WinS the circuit did not operate. We concluded that WRspice is more reliable.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.136-147
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• 2005

A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness ($t_{si}$ of 5 and $t_{sg}$ of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.23-36
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• 2004

A computationally efficient and accurate Monte Carlo (MC) simulator of electron beam lithography process has been developed for sub-0.l${\mu}{\textrm}{m}$ T-shaped gate formation in the HEMT devices for millimeter-wave frequencies. For the exposure process by electron to we newly and efficiently modeled the inner-shell electron scattering and its discrete energy loss with an incident electron for multi-layer resists and heterogeneous multi-layer targets in the MC simulation. In order to form the T-gate shape in resist layers, we usually use the different developer for each resist layer to obtain good reproducibility in the fabrication of HEMT devices. To model accurately the real fabrication process of electron beam lithography, we have applied the different developers in trilayer resist system By using this model we have simulated and analyzed 0.l${\mu}{\textrm}{m}$ T-gate fabrication process in the HEMT devices, and showed our simulation results with the SEM observations of the T-shaped gate process.

• Journal of the Korean Society of Radiology
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• v.13 no.5
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• pp.773-778
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• 2019

Images using X-rays are essential to diagnosis, but noise is inevitable in the image. To compensate for this, a total variation (TV) algorithm was presented to reduce the patient's exposure dose while increasing the quality of the images. The purpose of this study is to verify the effect on the image quality in radiographic imaging according to the thickness of the additional filtration plate through simulation, and to evaluate the usefulness of the TV algorithm. By using the Geant4 Application for Tomographic Emissions (GATE) simulation image, the actual size, shape and material of the Polymethylmethacrylate (PMMA) phantom were identical, the contrast to noise ratio (CNR) and coefficient of variation (COV) were compared. The results showed that the CNR value was the highest and the COV the lowest when applying the TV algorithm. In addition, we can acquire superior CNR and COV results with 0 mm Al in all algorithm cases.

• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.252-255
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• 2013

Nano MOS with $Er_2O_3/SiO_2$ double-layer gate dielectrics was demonstrated by EDISON Nanophysics software. Double-layer structure decreases the gate leakage current in two orders compared with $SiO_2$ single-layer gate dielectric.