• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.3
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• pp.177-182
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• 2013

Transparent thin film transistors (TTFT) were fabricated on $N^+$ Si wafers. $SiO_2$, $Si_3N_4/SiO_2$ and $Al_2O_3/SiO_2$ grown on the wafers were used as gate insulators. The rf magnetron sputtered zinc tin oxide (ZTO) films were adopted as active layers. $N^+$ Si wafers were wet-oxidized to grow $SiO_2$. $Si_3N_4$ and $Al_2O_3$ films were deposited on the $SiO_2$ by plasma enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD), respectively. The mobility, $I_{on}/I_{off}$ and subthreshold swing (SS) were obtained from the transfer characteristics of TTFTs. The properties of gate insulators were analyzed by comparing the characteristics of TTFTs. The property variation of the ZTO TTFTs with time were observed.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.2
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• pp.6-12
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• 1998

Thin film SOI(Silicon-on-insulator) device offer unique advantages such as reduction in short channel effects, improvement of subthreshold slope, higher mobility, latch-up free nature, and so on. But these devices exhibit floating-body effet such as current kink which inhibits the proper device operation. In this paper, the SOI NMOSFET with a T-type gate structure is proposed to solve the above problem. To simulate the proposed device with TSUPREM-4, the part of gate oxide was considered to be 30nm thicker than the normal gate oxide. The I-V characteristics were simulated with 2D MEDICI. Since part of gate oxide has different oxide thickness, the gate electric field strength is not same throughout the gate and hence the impact ionization current is reduced. The current kink effect will be reduced as the impact ionization current drop. The reduction of current kink effect for the proposed device structure were shown using MEDICI by the simulation of impact ionization current, I-V characteristics, and hole current distribution.

• Journal of Korea Society of Industrial Information Systems
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• v.12 no.2
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• pp.37-48
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• 2007

In order to become a mega hub port, major ports all over the world are making every effort to enhance their productivity through efficiency of internal operation and introduction of the state-of-the-art technologies. They are not only installing various kinds of high-technology equipments but also introducing advanced technologies for the development of an effective gate system. Recently thanks to the appearance of RFID (radio frequency identification) and OCR (optical character recognition) technology, major container terminals are stewing up the automation of truck and container identification at the container luminal gate. This study aim to develop an automated gate system for identification task based on RFID and OCR technology. It will make mn effective gate operations in a container terminal.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2070-2078
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• 2014

In this work, the frequency response of gate-all-around (GAA) Ge/GaAs heterojunction tunneling field-effect transistor (TFET) with hetero-gate-dielectric (HGD) and pnpn channel doping profile has been analysed by technology computer-aided design (TCAD) device-circuit mixed-mode simulations, with comparison studies among ppn, pnpn, and HGD pnpn TFET devices. By recursive tracing of voltage transfer curves (VTCs) of a common-source (CS) amplifier based on the HGD pnpn TFET, the operation point (Q-point) was obtained at $V_{DS}=1V$, where the maximum available output swing was acquired without waveform distortion. The slope of VTC of the amplifier was 9.21 V/V (19.4 dB), which mainly resulted from the ponderable direct-current (DC) characteristics of HGD pnpn TFET. Along with the DC performances, frequency response with a small-signal voltage of 10 mV has been closely investigated in terms of voltage gain ($A_v$), unit-gain frequency ($f_{unity}$), and cut-off frequency ($f_T$). The Ge/GaAs HGD pnpn TFET demonstrated $A_v=19.4dB$, $f_{unity}=10THz$, $f_T=0.487$ THz and $f_{max}=18THz$.

• Journal of the Society of Naval Architects of Korea
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• v.45 no.6
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• pp.611-619
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• 2008

In most shipyards Floating Dock-gate System is adapted for dry docks. For the safe launching of ships in dry docks, smooth operation of dock-gate must be guaranteed. So it is very important to grasp its behavior in waves for securing the high productivity and the safety of workers. Its seakeeping ability was estimated numerically at the floating conditions and the free roll decay and the seakeeping model tests of dock-gate was carried out with bilge-keels of 3 different widths which have a scale of 1 to 20. More than 20% decrease of roll motion was observed in irregular beam seas by applying a bilge-keel system to the dock-gate that is long and narrow.

• 한국방재학회:학술대회논문집
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• 2008.02a
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• pp.791-794
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• 2008

The transport and dispersion of pollutants in natural river is a principal issue in intake station management. To study the pollutant transport in natural rivers, the effect of meandering and confluence of tributary on mixing process have to analyzed. The objective of this study is to simulate the mixing and transport of pollutants for operating water gate of Nakdong Estuary Barrage around the intake station. Mulgeum intake station being used as drinking water sources for Pusan. The flow around the intake station is influenced by operating water gate of Nakdong Estuary Barrage which is located downstream. The water gate system includes ten individual gates. The minor gate is usually opened according to elevation of the sea. When the river flow increases, the main water gate is opened. Daepo stream, tributary of the Nakdong river, is on opposite side of the intake station. The pollutants from Daepo stream often flows into the intake station acoording to the flow pattern. In this study, based on this simulation results, proper water gate operation which can minimize negative impact will be provided.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.96-96
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• 2007

Low voltage organic TFTs (OTFTs) and ZnO based TFTs (<5V), utilizing room temperature deposited $Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7$ (BZN) thin films were recently reported, pointing to high-k gate insulators as a promising route for realizing low voltage operating flexible electronics. $Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7$ (BZN) thin film is one of the most promising materials for gate insulator because of its large dielectric constant (~60) at room temperature. However their tendency to suffer from relatively high leakage current at low electric field (>0.3MV/cm) hinder the application of BZN thin films for gate insulator. In order to improve leakage current characteristics of BZN thin film, we mixed 30mol% MgO with 70mol% BZN and their dielectric and electric properties were characterized. We fabricated field-effect transistors with transparent oxide semiconductor ZnO serving as the electron channel and high-k $(Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7)_{0.7}(MgO)_{0.3}$ as the gate insulator. The devices exhibited low operation voltages (<4V) due to high capacitance of the $(Bi_{1.5}Zn_{1.0}Nb_{1.5}O_7)_{0.7}(MgO)_{0.3}$ dielectric.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.1
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• pp.87-96
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• 2019

Flexible organic light-emitting diode (OLED) displays with organic thin-film transistors (OTFTs) backplanes have been studied. A gate driver is required to drive the OLED display. The gate driver is integrated into the panel to reduce the manufacturing cost of the display panel and to simplify the module structure using fabrication methods based on low-temperature, low-cost, and large-area printing processes. In this paper, pseudo complementary metal oxide semiconductor (CMOS) logic gates are implemented using OTFTs for the gate driver integrated in the flexible OLED display. The pseudo CMOS inverter and NAND gates are designed and fabricated on a flexible plastic substrate using inkjet-printed OTFTs and the same process as the display. Moreover, the operation of the logic gates is confirmed by measurement. The measurement results show that the pseudo CMOS inverter can operate at input signal frequencies up to 1 kHz, indicating the possibility of the gate driver being integrated in the flexible OLED display.

• Journal of Navigation and Port Research
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• v.46 no.4
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• pp.344-350
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• 2022

Due to the increase in container cargo volume, the congestion of container terminals is increasing and the waiting time of gate in-out trucks has significantly lengthened at container yards and gates, resulting in severe inefficiency in gate in-out truck operations as well as port operations. To resolve this problem, the Busan Port Authority and terminal operator provide services such VBS, terminal congestion information, and expected operation processing time information. However, the visible effect remains insufficient, as it may differ from actual waiting time.. Thus, as basic data to resolve this problem, this study presents deep learning based average gate in-out truck waiting time prediction models, using container gate in-out information at Busan New Port. As a result of verifying the predictive rate through comparison with the actual average waiting time, it was confirmed that the proposed predictive models showed high predictive rate.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.11
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• pp.56-62
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• 1999

All the cells on the whole memory array or a block of the memory array in the Flash EEPROM's are erased at the same time using Fowler-Nordheim (FN) tunneling. some of the cels are often overerased since the tunneling is not a self-limited process. In this paper, the optimum doping concentration of the floating gate solve the overerase problem has been studied. For these studies, N-type MOSFETs and MOS capacitors with various doping concentrations of the gate polysilicon have been fabricated and their electrical characteristics have been measured and analyzed. As the results of the experiment, it has been found that the overerase problem can be prevented if the doping concentration of the floating gate is low enough (i.e. below $1.3{\times}10^{18}/cm^3$). It is because the potential difference between the floating gate and the source is lowered due to the formation of the depletion layer in the floating gate and thus the erasing operation stops by itself after most of the electrons stored in the floating gate are extracted. On the other hand, the uniformity of the Vt and the gm has been significantly poor if the coping concentration of the floating, gate is too much lowered (i.e. below $1.3{\times}10^{17}/cm^3$), which is believed to be due to nonuniform loss of the dopants from the nonuniform segregation in the floating gate. Consequently, the optimum doping concentration of the floating gate to suppress the overerase problem and get the uniform Vt and has been found to range from $1.3{\times}10^{17}/cm^3$ to $1.3{\times}10^{18}/cm^3$ in the Flash EEPROM.