• 한국정보통신학회논문지
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• 제22권1호
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• pp.117-124
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• 2018

박막 두께가 다른 무접합 비정질 InGaZnO 막막 트랜지스터를 제작하고 박막 두께, 동작 온도 및 빛의 세기에 따른 소자의 성능 변수를 추출하고 게이트 산화층 항복전압을 분석하였다. 박막의 두께가 클수록 소자의 성능이 우수하나 드레인 전류의 증가로 게이트 산화층 항복전압은 감소하였다. 고온에서도 소자의 성능은 개선되었으나 게이트 산화층 항복 전압은 감소하였다. 빛의 세기가 증가할수록 광자에 의해 생성된 전자로 드레인 전류는 증가 하였으나 역시 게이트 산화층 항복전압은 감소하였다. 박의 두께가 클수록, 고온일수록, 빛의 세기가 강할수록 채널의 전자수가 증가하여 산화층으로 많이 주입되었기 때문이다. 무접합 a-IGZO 트랜지스터를 BEOL 트랜지스터로 사용하기 위해서는 박막 두께 및 동작 온도를 고려해서 산화층 두께를 설정해야 됨을 알 수 있었다.

• 한국철도학회논문집
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• 제20권3호
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• pp.339-348
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• 2017

철도차량용 전원창치는 추진제어용 전원장치와 보조전원장치로 구분된다. 추진제어용 전원장치는 철도차량의 추진 및 회생제동 등의 동작을 위한 것이며, 보조전원장치는 추진제어용 전원을 제외한 공기압축기, 조명기기, 차량제어전원 등의 보조전원에 사용되는 것이다. 각 전원장치는 고전압, 고전류 사양 특성에 따라 일반적으로 insulated-gate bipolar transistor (IGBT)를 스위칭 소자로 사용하고 있다. 스위칭 소자를 사용하기 위해서는 적절한 스위칭 동작을 구현하기 위한 구동회로(Gate Driver Unit, GDU)가 필수적이다. 본 논문에서는 철도차량에 적용되고 있는 IGBT용 GDU에 적용되고 있는 기술 동향을 분석하고 철도차량용 IGBT GDU 설계 시 고려사항에 대해 알아보고자 한다.

• 대한토목학회논문집
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• 제26권3D호
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• pp.367-374
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• 2006

본 연구에서는 국내 철도건널목의 지장물 검지 시스템 및 차단제어 시스템의 운영현황을 살펴봄으로써 기존 시스템의 문제점을 보완할 수 있는 새로운 건널목 제어시스템 및 알고리즘을 제시한다. 국내 건널목 제어시스템의 경우 차량 및 지장물 검지를 통해 단순 입구측 및 출구측을 제어하는 방식으로서 도로 교통과는 연계를 하지 못하고 있는 실정이다. 또한 검지시스템과 차단시스템의 신호연계체계의 미비로 인하여 비효율적이며 안전성이 결여된 건널목 운영을 보이고 있다. 본 연구에서는 보다 효율적인 건널목 운영을 위하여 지자계 검지센서와 레이저 검지센서를 통합한 철도 건널목 지장물 진입위반차량 검지시스템과 4분할차단기 알고리즘을 제시하였고, 현장시험을 통하여 본 연구에서 제시한 알고리즘의 신뢰성을 검증하였다. 그 결과 본 연구에서 개발되어진 시스템들은 철도 건널목 제어기기들간의 상호연계가 가능하며, 동시에 차량운전자의 운행 형태를 고려한 차단제어 방식으로 열차와의 충돌사고를 예방할 수 있으리라 기대되어진다.

• ETRI Journal
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• 제38권4호
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• pp.645-653
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• 2016

This paper demonstrates the performance of a metal-substrate power module with multiple fabricated chips for a high current electrical application, and evaluates the proposed module using a 1.5-kW sinusoidal brushless direct current (BLDC) motor. Specifically, the power module has a hybrid structure employing a single-layer heat-sink extensible metal board (Al board). A fabricated motor driver IC and trench gate DMOSFET (TDMOSFET) are implemented on the Al board, and the proper heat-sink size was designed under the operating conditions. The fabricated motor driver IC mainly operates as a speed controller under various load conditions, and as a multi-phase gate driver using an N-ch silicon MOSFET high-side drive scheme. A fabricated power TDMOSFET is also included in the fabricated power module for three-phase inverter operation. Using this proposed module, a BLDC motor is operated and evaluated under various pulse load tests, and our module is compared with a commercial MOSFET module in terms of the system efficiency and input current.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.829-832
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• 2005

This paper describes a wide-range dual-loop Delay Locked Loop (DLL) using Voltage Controlled Delay Line (VCDL) based on Transmission Gate(TG) inverters. One loop is used when the minimum VCDL delay is greater than a half of $T_{REF}$, the reference clock period. The other loop is initiated when the minimum delay is less than $0.5{\times}T_{REF}$. The proposed VCDL improves the dynamic operation range of a DLL. The DLL with a VCDL of 10 TG inverters provides a lock range from 70MHz to 700MHz when designed using $0.18{\mu}m$ CMOS technology with 1.8 supply voltage. The DLL consumes 11.5mW for locking operation with a 700MHz reference clock. The proposed DLL can be used for high-speed memory devices and processors, communication systems, high-performance display interfaces, etc.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 전력전자학술대회 논문집
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• pp.361-362
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• 2016

Presented in this paper is the design of a high voltage switch module made up of MOSFETs, pulse transformers and their gate driver circuits compactly fitted onto a single PCB module. The ease by which the switch modules can be configured (series stacking and/or parallel stacking) to meet future load variations allows for flexible operation of this design. In addition, the detailed implementation of the gate driver circuit for reliable and easier switch synchronization is also described in this paper. The stored energy in the capacitor bank of a 15kV, 4.5kJ/s peak power capacitor charger was discharged using the developed high voltage switch, and by experimental results, the operation of the proposed circuit was verified to be effectively used as a switch for pulse discharging.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2011년도 제42회 하계학술대회
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• pp.1580-1581
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• 2011

The linear accelerator of Pohang Accelerator Laboratory(PAL) will drive a top-up mode operation in PLS-II(Pohang Light Source-II). Due to this kind of the operation mode, the electron gun is expected to have shorter life time of the cathode. Further in the PLS-II, two gate valves will be installed in front of the electron gun. The distance between the pre-bunching section and the electron gun will increase by 400 mm compared to the existing system due to the insertion of these gate valves. As a result the incident electron beam. One of the goals to improve the beam pulse width is by incorporating suitable biased voltage. In this paper, we will present test results of beam pulse width as a function of different biased voltage and focusing solenoid coil.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.875-878
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• 1998

In this thesis, we present efficient techniques to reduce the switching activity in a CMOS combinational logic network based on local logic transforms. But this techniques is not appropriate in the view of testability because of deteriorating the random pattern testability of a circuit. This thesis proposes a circuit design method having two operation modes. For the sake of power dissipation(normal operation mode), a gate output switches as rarely as possible, implying highly skewed signal probabilities for 1 or 0. On the other hand, at test mode, signals have probabilities of being 1 or 0 approaching 0.5, so it is possible to exact both stuck-at faults on the wire. Therefore, the goals of synthesis for low power and random pattern testability are achieved. The hardware overhead sof proposed design method are only one primary input for mode selection and AND/OR gate for each redundant connection.

• 반도체디스플레이기술학회지
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• 제5권1호
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• pp.17-20
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• 2006

This paper presents of a new type of memory cell that could potentially replace both DRAM and flash memory. The proposed device cell operates by sensing the state of about 1,000 electrons trapped between unique insulating barriers in the channel region of the upper transistor. These electrons are controlled by a side gate on the transistor, and their state in turn controls the gate of the larger transistor, providing signal gain within the memory cell. It becomes faster and more reliable memory with lower operation voltage. Moreover, the use of a multiple tunnel junction (MTJ) fur the vertical transistor can significantly improve the data retention and operation speed.

• Progress in Superconductivity
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• 제4권1호
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• pp.37-41
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• 2002

In this work. we have designed two different kinds of Rapid Single Flux Quantum (RSFQ) OR-gates. One was based on the already developed RSFQ cells and the other was aimed to develop a more compact version. In the first circuit, we used a combination of two D Flip-Flops and a merger and in the other circuit we used a combination of RS Flip-Flops and Confluence Buffer. We tested the circuit performance by using the simulation tools, Xic and Wrspice. We obtained the operation margins of the circuit elements by a margin calculation program, and we obtained the minimum operation margins of $\pm$30%. The circuits were laid out, aimed to fabricate by using the existing KRISS Nb process. KRISS Nb process includes the $Nb／Al_2$$O_3$／Nb trilayer fabricated by DC magnetron sputtering and the reactive ion etching technique for the definition of the features. The major tools used in the layouts were Xic and L-meter.