• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.184-187
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• 2002

In this work, the electrical characteristics of organic thin film transistors with the stacked organic gate insulators have been studied. PVP(Polyvinylphenol) and polystyrene were used as gate insulating materials. Both the high dielectric constant of PVP and better insulating capability of polystyrene were compensatorily adopted in two different stacking orders of PVP-polystyrene and polystyrene-PVP. The output characteristics of the device with the stacked gate insulator showed substantial improvement compared with those of the devices with either PVP or polystyrene gate insulator: Furthermore, these stacked organic gate insulators can differently affect the TFT characteristics with the stacking orders. The electrical properties of TFTs with organic gate insulators stacked in different orders are discussed.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.439-442
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• 1990

GaAs MESFETs with the submicron gat are fabricated. $G_{m,mas}$ = 195mS/mm with the $0.5{\mu}m$ gate length and $G_{m,mas}$ = 170mS/mm with the $0.6{\mu}m$ gate lenth. $f_{mas}$ = 7GHz with the $1.5{\mu}m$ gate length and the $120{\mu}m$ gate width. We can estimate that $f_{mas}$ = 15GHz with $0.6{\mu}m$ gate length and that $f_{mas}$ = 18 ${\sim}$ 20GHz with the $0.5{\mu}m$ gate length.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.157-158
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• 2000

In this study, to get the larger drain current of the device under the same operation condition as the conventional gate dielectric SiNx thin film transistor devices, we introduced new gate dielectric $Ta_2O_5$ thin film which has high dielectric constant $({\sim}25)$ and good electrical reliabilities. For the application for the TFT device, we fabricated the $Ta_2O_5$ gate dielectric TFT on the low-temperature-transformed polycrystalline silicon thin film using the self-aligned implantation processing technology for source/drain and gate doping. The $Ta_2O_5$ gate dielectric TFT showed better electrical performance than SiNx gate dielectric TFT because of the higher dielectric constant.

• Proceedings of the Safety Management and Science Conference
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• 2001.11a
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• pp.37-42
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• 2001

Utilization rate for the restrictive gate and required time and walking distance to board are to be a measure for the gate management and passenger's convenience estimation. So, the main purpose of the gate management are maximization of utilization rate and increment of airport terminal user's convenience through the efficient gate management. This study intends to maximize the utilization rate on usable gates by concerning about layout, terminal configuration, local passenger of the airport and development of gate assignment algorithm and DSS which maximize the gate utilization and minimize the passenger's walking distance.

• Journal of the Korea Safety Management & Science
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• v.5 no.1
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• pp.93-102
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• 2003

Utilization rate for the gate and required time and walking distance to boarding flight are important measures for the gate management and passenger's convenience estimation. So, the main purpose of the gate management are the maximization of utilization rate and improvement of airport terminal user's convenience through the efficient gate management. This study intends to maximize the utilization rate of usable gates by considering layout, terminal configuration, local passenger of the airport and development of gate assignment algorithm and DSS which maximizes the gate utilization and minimizes the passengers' walking distance. And the decision support system can provide an efficient means of airport management of airport using an assignment algorithm.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1243-1246
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• 2009

A novel a-Si TFT integrated gate driver circuit which suppresses the threshold voltage shift due to prolonged positive gate bias to pull-down TFTs, is reported. Negative gate-to-drain bias is applied alternately to the pull-down TFTs to recover the threshold voltage shift. Consequently, the stability of the circuit has been improved considerably.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1333-1335
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• 2000

In order to turn on the SCR gate, trigger signal source have to provide appropriate gate current and voltage under the gate rating based on the characteristic of SCR, the nature of load and power. It will be essential design factors such as trigger source impedance, trigger signal occurring, signal time width and turn off conditions. Also minimum gate trigger current is changed with the deterioration of SCR. SCR, which is needed large gate trigger current absolutely, is very important for SCR characteristic test because it causes unstable output in the misfile or makes a trouble to pulse trigger circuits. This paper shows scheme to test the performance of SCR with the precision analyzing mechanism and the changing trend of minimum gate current under the trigger conditions.

• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.6
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• pp.246-250
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• 2005

The forward voltage drop of IGBT is studied numerically and analytically as a function of gate length. An analytical expression is presented for the first time for the surface potential variation along the channel layer under the gate of IGBT. The surface potential drop and the carrier density near the surface allow calculation of the forward voltage drop of IGBT analytically as a function of the gate length. The voltage-drop in the drift region near the gate decreases exponentially, whereas that on the surface increases linearly with increasing the gate length, the sum of which exhibits an optimum gate length, resulting in a minimum forward voltage drop. Based on the surface potential drop, a remodelling of the forward voltage drop of IGBT is also proposed.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.05a
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• pp.24-28
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• 2004

본 연구는 기존에 제안한 방전 AND gate PDP의 결점을 개선한 연구로써 AND gate를 구성하는 DC 방전의 극성을 반대로 설계하여 인접 주사전극에 대한 cross talk를 개선하였다. 또한 기존의 AND gate가 공간전하에 의한 방전의 비선형성에 의존한 것과는 달리 본 연구에서 제안한 AND gate는 방전 경로에 따른 전압의 변화에 의존하는 것으로 AND gate의 동작이 한층 안정해 졌다. 실험 결과 4개의 수평 주사전극에 대해 선택적인 어드레스 방전이 가능하였으며 각각 34V와 70V의 AND 방전 및 Data 방전의 동작마진을 얻을 수가 있었다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.9
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• pp.523-526
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• 2000

A dual gate trench emitter IGBT structure is proposed and studied numerically using the device simulator MEDICI. The on-state forward voltage drop latch-up current density turn-off time and breakdown voltage of the proposed structure are compared with those of the conventional DMOS-IGBT and trench gate IGBT structures. The proposed structure forms an additional channel and increases collector current level resulting in reduction of on -state forward voltage drop. In addition the trench emitter increases latch-up current density by 148% in comparison with that for the conventional DMOS-IGBT and by 83% compared with that for the trench gate IGBT without degradation in breakdown voltage when the half trench gate width(Tgw) and trench emitter depth(Ted) are fixed at $1.5\mum\; and\; 2\mum$, respectively