• Proceedings of the Computational Structural Engineering Institute Conference
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• 1997.04a
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• pp.79-86
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• 1997

In this study, pre-postprocessing toolbox is developed to perform elasto-plastic analyze of underground structures with transient ground water flow. This toolbox is composed of three modules. The first is the data input processor for the structural analysis. The preprocessing Is using GUI (Graphic User Interface), which is consist of dialog box, pull down, and short-cut icon, etc. The second is the structural analysis module. The analysis is based on the elasto-plastic finite element method involving additional options such as ground excavation effect, transient ground water flow, and rock bolts behavior. The last is the postprocessing module. The postprocessing is able to verify the result of the structural analysis by the graphical simulation which visualizes the element mesh, the node displacements, the element stress states, the stress contour, the ground water surface, and the rock bolt stresses. Since various options are considered separately in this toolbox, it is easy to modify the module of each processing, and to update other functional modules for the given analysis conditions.

• Journal of the Korea Society for Simulation
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• v.18 no.4
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• pp.117-125
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• 2009

Recently the intelligent agent systems have been emerged as one of key issues for developing the defense M&S systems. However, most conventional agent architecture of M&S systems utilize the script-based models and can only deal with the individual behaviors so that they cannot suitably describe the precise tactical/strategic behavior and/or complex warfare environment. To overcome these problems, we have proposed the hierarchical multi-agent system architecture that is able to intelligently cope with the complex missions based on the functional role of each agent on the hierarchy such as an intelligence officer, captain, warship commander. Several simulation tests performed on 2:2 warship warfare models will illustrate our techniques.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.10
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• pp.2123-2135
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• 1997

In this paepr, we consider resistive shorts on drain-source, drain-gate, and gate-source as well as opens in MOSFETs included in typical memory cell of VLSI SRAM. Behavior of memeory is observed by analyzing voltage at storage nodes of memeory and IDDQ(quiescent power supply current) through PSPICE simulation. Using this behavioral analysis, an effective testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ testing simultaeously is proposed. Built-In Self Test(BIST) circuit which detects faults in memories and Built-In Current Sensor(BICS) which monitors the power supply bus for abnormalities in quescent current are developed and imprlemented to improve the quality and efficiency of testing. Implemented BIST and BICS circuits can detect locations of faults and defects in order to repair faulty memories.

• Journal of Electrical Engineering and Technology
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• v.1 no.4
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• pp.472-481
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• 2006

In the conventional SRM with multi-rotor teeth, the air gap must be very small in order to drive the SRM in the saturation region that is necessary for high output torque. However, this leads to the problem of overheating; particularly in the case of a small-size SRM This paper discusses the design of a new type of SRM, namely the rolled rotor SRM. This new type does not require more than a single region of a very small airgap. This solves the overheating problem in the small size SRM. Moreover, the use of the rolled rotor, instead of the conventional toothed rotor, grades the airgap region in a fashion that gives a smooth variation in the reluctance and smooth shapes of both current and torque. The latter functional behavior is required in many applications such as servo applications. The paper first addresses general design steps of the rolled rotor SRM then proceeds to the simulation results of the new SRM in order to evaluate the advantages gained from the new design. In addition, this paper compares the torque ripples obtained from the new design to its equivalent conventional one.

• Journal of the Korean Institute of Intelligent Systems
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• v.13 no.3
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• pp.287-292
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• 2003

The ability of robot is being various and complex. The robot is utilizing distance, image data and voice data for sensing its circumstance. This paper suggests the 2-layer fuzzy control as the algorithm that control robot with various sensor information. In a obstacle avoidance, it utilizes many range finders and classifies them into 3parts(front, left, right). In 3 sub-controllers, the controller executes fuzzy conference. And then it executes combined control with a combination of outputs of 3 sub-controllers in the second step. The text compares the 2-layer fuzzy controller with the hierarchical fuzzy controller that has analogous structure. And the performance of the 2-layer fuzzy controller is confirmed by application this controller to robot following, simulation to each other and real experiment.

• International Journal of Highway Engineering
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• v.8 no.4 s.30
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• pp.1-11
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• 2006

Currently, road mobility improved from the National Road Improvement. Nevertheless delineation system is facility that enhanced driver's safety, that was set up often inconsistent or nonexistent over the road exit ramp So it judged functional investigation will be necessary. This study suggested setting type of the delineation system. That was based on a field study and reviews the legal standard of it and considering driver's cognition behavior. For the study, make a 3D-simulation and so could objectively a comparative test. Comparison variable between delineation setting type is selected conspicuity and visibility. Cased that illustrated characteristics of driver's visual cognition behavior. The experiment was used Eye Marker Recorder for measure the gaze frequency more quantitatively and objectively. And used the ANOVA analysis for significance testing between delineation setting type. A significant percent of the conspicuity analyzed types(Safe mark, Obstacle Sign, Warning Light, and Tubular Maker) in road exit ramp for recognize. And gaze frequency that measure of effectiveness of visibility are measured. On the analysis result, the visibility was significance difference between delineation setting type and visibility of types was best.

• Journal of Korean Society of Transportation
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• v.20 no.3
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• pp.149-158
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• 2002

For the purpose of preciously describing real time traffic pattern in urban road network, dynamic network loading(DNL) models able to simulate traffic behavior are required. A number of different methods are available, including macroscopic, microscopic dynamic network models, as well as analytical model. Equivalency minimization problem and Variation inequality problem are the analytical models, which include explicit mathematical travel cost function for describing traffic behaviors on the network. While microscopic simulation models move vehicles according to behavioral car-following and cell-transmission. However, DNL models embedding such travel time function have some limitations ; analytical model has lacking of describing traffic characteristics such as relations between flow and speed, between speed and density Microscopic simulation models are the most detailed and realistic, but they are difficult to calibrate and may not be the most practical tools for large-scale networks. To cope with such problems, this paper develops a new DNL model appropriate for dynamic traffic assignment(DTA), The model is combined with vertical queue model representing vehicles as vertical queues at the end of links. In order to compare and to assess the model, we use a contrived example network. From the numerical results, we found that the DNL model presented in the paper were able to describe traffic characteristics with reasonable amount of computing time. The model also showed good relationship between travel time and traffic flow and expressed the feature of backward turn at near capacity.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.43-51
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• 2014

In 3-dimensional (3D) integrated package, thermal management is one of the critical issues due to the high heat flux generated by stacked multi-functional chips in miniature packages. In this study, we used numerical simulation method to analyze the thermal behaviors, and investigated the thermal issues of 3D package using TSV (through-silicon-via) technology for mobile application. The 3D integrated package consists of up to 8 TSV memory chips and one logic chip with a interposer which has regularly embedded TSVs. Thermal performances and characteristics of glass and silicon interposers were compared. Thermal characteristics of logic and memory chips are also investigated. The effects of numbers of the stacked chip, size of the interposer and TSV via on the thermal behavior of 3D package were investigated. Numerical analysis of the junction temperature, thermal resistance, and heat flux for 3D TSV package was performed under normal operating and high performance operation conditions, respectively. Based on the simulation results, we proposed an effective integration scheme of the memory and logic chips to minimize the temperature rise of the package. The results will be useful of design optimization and provide a thermal design guideline for reliable and high performance 3D TSV package.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.15-25
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• 2012

The research on the FPGA CAD tools in academia has been lacking practicality due to the underlying FPGA fabric architecture which is too simple and inefficient to be applied for commercial FPGAs. Recently, the database of placement positions and routing graphs on commercial FPGA architectures has been built, and provided for enabling the academic development of placement and routing tools. To extend the limit of academic CAD tools even further, we have developed the evaluation toolkit for the K-FPGA architecture which is under development. By providing interface for exchanging data with a commercial FPGA toolkit at every step of mapping, packing, placement and routing in the tool chain, the toolkit enables individual tools to be developed without waiting for the results of the preceding step, and with no dependency on the quality of the results, and compared in detail with commercial tools at any step. Also, the fabric primitive library is developed by extracting the prototype from a reporting file of a commercial FPGA, restructuring it, and modeling the behavior of basic gates. This library can be used as the benchmarking target, and a reference design for new FPGA architectures. Since the architecture is described in a standard HDL which is familiar with hardware designers, and read in the tools rather than hard coded, the tools are "data-driven", and tolerable with the architectural changes due to the design space exploration. The experiments confirm that the developed library is correct, and the functional correctness of applications implemented on the FPGA fabric can be validated by simulation. The placement and routing tools are under development. The completion of the toolkit will enable the development of practical FPGA architectures which, in return, will synergically animate the research on optimization CAD tools.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.37-47
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• 2011

Real picture like high quality computer graphic is widely used in various fields and shader processor, a key part of a graphic processor, has been advanced to programmable unified shader. However, The existing graphic processors have been optimized to commercial algorithms, so development of an algorithm which is not based on it requires an independent shader processor. In this paper, we have designed and implemented a control unit to support high quality 3 dimensional computer graphic image on programmable integrated shader processor. We have done evaluation through functional level simulation of designed control unit. Hardware resource usage rate are measured by implementing directly on FPGA Virtex-4 and execution speed are verified by applying ASIC library. the result of an evaluation shows that the control unit has the commands more about 1.5 times compared to the other shader processors that is a behavior similar to the control unit and with a number of processing units used in a shader processor, compared with the other processors, overall performance of the control unit is improved about 3.1 GFLOPS.