• Journal of Korean Library and Information Science Society
• /
• v.40 no.4
• /
• pp.199-225
• /
• 2009

The purpose of this paper is to grow more interest and to forster research in full-texts retrieval of digitized books area through the review of Book Search Track and the analysis of research methods. First, this paper introduces the INEX tracks, the registration of INEX, the task process and the participating organizations. Second, to introduce the Book Search Track of all INEX tracks, this paper provides an overview of the test collection, the tasks, the task and submission guidelines and evaluation results of the Book Search Track's. Third, through paper review of the Book Search track that was lunched in 2007 as part of the INEX initiative, this paper presents the future research subject. This study expects that the readers are attracted by INEX tracks and full-texts retrieval of digitized books in korea.

• Journal of Korea Multimedia Society
• /
• v.8 no.8
• /
• pp.1080-1087
• /
• 2005

Significant computations for full search (FS) motion estimation have been a big obstacle in real-time video coding and recent MPEG-4 AVC (advanced video coding) standard requires much more computations than conventional MPEG-2 for motion estimation. To reduce an amount of computation of full search (FS) algorithm for fast motion estimation, we propose a new and fast matching algorithm without any degradation of predicted images like the conventional FS. The computational reduction without any degradation in predicted image comes from fast elimination of impossible candidate motion vectors. We obtain faster elimination of inappropriate motion vectors using efficient matching units from localization of complex area in image data and dithering order based matching scan. Our algorithm reduces about $30\%$ of computations for block matching error compared with the conventional partial distortion elimination (PDE) algorithm, and our algorithm will be useful in real-time video coding applications using MPEG-4 AVC or MPEG-2.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.30 no.3
• /
• pp.405-415
• /
• 2020

With the increase in smartphone user, mobile forensics has become an essential element in modern digital forensic investigation. Mobile messenger data is very important data in mobile forensics because it can acquire information such as user's life pattern and mental state. In order to analyze messenger data, a decryption technique of an encrypted messenger data is required. Since most messengers provide a message deleting function, a technique for recovering deleted messages is required. WeChat Messenger, a messenger used by about 1 billion people around the world, uses IMEI (International Mobile Equipment Identity) information to encrypt data and provides message deletion function. In this paper, we propose a data decryption method in the absence of IMEI information and propose a method for recovering deleted messages using FTS (Full Text Search) database created for full-text search function of SQLite database.

• Journal of the Institute of Convergence Signal Processing
• /
• v.21 no.2
• /
• pp.55-60
• /
• 2020

In this paper, we propose a fast block matching algorithm of motion estimation using early detection of optimal candidate with high priority and a threshold. Even though so many fast algorithms for motion estimation have been published to reduce computational reduction full search algorithm, still so many works to improve performance of motion estimation are being reported. The proposed algorithm calculates block matching error for each candidate with high priority from previous partial matching error. The proposed algorithm can be applied additionally to most of conventional fast block matching algorithms for more speed up. By doing that, we can find the minimum error point early and get speed up by reducing unnecessary computations of impossible candidates. The proposed algorithm uses smaller computation than conventional fast full search algorithms with the same prediction quality as the full search algorithm. Experimental results shows that the proposed algorithm reduces 30~70% compared with the computation of the PDE and full search algorithms without any degradation of prediction quality and further reduces it with other fast lossy algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.8
• /
• pp.1531-1536
• /
• 2016

In this paper, we propose a fast motion estimation algorithm which is important in performance of video encoding. Even though so many fast algorithms for motion estimation have been published due to its tremendous computational amount of for full search algorithm, efforts for reducing computations in motion estimation still remain. In the paper, we propose an algorithm that reduces unnecessary computations only, while keeping prediction quality the same as that of the full search. The proposed algorithm does not calculate block matching error for each candidate at once to find motion vectors but divides the calculation procedure into several steps and calculates partial sum of block errors. By doing that, we can estimate the minimum error point early and get the enhancement of calculation speed by reducing unnecessary computations. The proposed algorithm uses smaller computations than conventional fast search algorithms with the same prediction quality as full search.

• Korean Journal of Cognitive Science
• /
• v.16 no.1
• /
• pp.1-15
• /
• 2005

Since human visual system has limited capacity for visual information processing, it should select goal-relevant information for further processing. There have been several studies that emphasized the possible involvement of memory in spatial shift of selective attention (Chun & Jiang, 1998, 1999; Klein, 1988; Klein & MacInnes, 1999). However, other studies suggested the inferiority of human visual memory in change detection(Rensink, O'Regan, & Clark, 1997; Simons & Levin, 1997) and in visual search(Hotowitz & Wolfe, 1998). The present study examined the involvement of memory in visual search; whether memory for the previously searched items guides selective attentional shift or not. We investigated how search works by comparing visual search performances in three different conditions; full exposure condition, partial exposure condition, and partial-to-full exposure condition. Revisiting searched items was allowed only in full exposure condition and not in either partial or partial-to-full exposure condition. The results showed that the efficiencies of attentional shift were nearly identical for all conditions. This finding implies that even in full exposure condition the participants scarcely re-examined the previously searched items. The results suggest that instant memory can be formed and used in visual search process. These results disagree with the earlier studies claiming thar visual search has no memory. We discussed the problems of the previous research paradigms and suggested some alternative accounts.

• Journal of Korea Multimedia Society
• /
• v.14 no.10
• /
• pp.1275-1286
• /
• 2011

This paper proposes a high speed systolic array architecture for full search block matching algorithm (FBMA). The pixels of the search area for a reference block are input only one time to find the matched candidate block and reused to compute the sum of absolute difference (SAD) for the adjacent candidate blocks. Each row of designed 2-dimensional systolic array compares the reference block with the adjacent blocks of the same row in search area. The lower rows of the designed array get the pixels from the upper row and compute the SAD with reusing the overlapped pixels of the candidate blocks within same column of the search area. This designed array has no data broadcasting and global paths. The comparison with existing architectures shows that this array is superior in terms of throughput through it requires a little more hardware.

• Proceedings of the Korean Information Science Society Conference
• /
• 2006.10a
• /
• pp.153-157
• /
• 2006

기존의 탐색 알고리즘은 탐색 창 내의 원점에서 탐색을 시작한다. 하지만 영상은 일정한 방향으로 규칙적으로 움직이는 것이 많기 때문에 Frame$_t$ 의 움직임 벡터(MV)가 Frame$_{t-1}$의 움직임 벡터와 같을 가능성이 크다. 이를 참고하여 본 논문에서는 시작점을 원점뿐만 아니라 Frame$_{t-1}$의 MV까지도 예측 시작점으로 선택하여 탐색의 시작점을 다양화 하였다. 실험 결과 탐색 시작점을 다양화 함으로써 full search를 제외한 diamond search, hexagonal search, 4 step search등 기존의 탐색 알고리즘보다 30$\sim$80% 더 작은 SAD값을 구할 수 있었다.

• Journal of the Institute of Convergence Signal Processing
• /
• v.16 no.4
• /
• pp.129-133
• /
• 2015

In this paper, we propose a fast motion estimation algorithm which is important in the performance of video encoding. Conventional fast motion estimation algorithms have serious problems of low prediction quality in some frames and still much computation. In the paper, we propose an algorithm that reduces unnecessary computations only, while keeping prediction quality almost similar to that of the full search. The proposed algorithm uses distribution of probability of motion vectors, divides search range into several groups according to its importance, and applies adaptive block matching criteria for each group of search range. The proposed algorithm takes only 3~5% in computational amount and has decreased prediction quality about 0~0.01dB compared with the fast full search algorithm.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.12
• /
• pp.110-119
• /
• 1996

A novel high speed VLSI architecture and its VLSI realization methodologies for a motion estimation processor based on full search block matching algorithm are presentd. The presented architecture is designed in order to be suitable for highly parallel and pipelined processing with identical PE's and adjustable in performance and hardware amount according to various application areas. Also, the throughput is maximized by enhancing PE utilization up to 100% and the chip pin count is reduced by reusing image data with embedded image memories. Also, the uniform and identical data processing structure of PE's eases VLSI implementation and the clock rate of external I/O data can be made slower compared to internal clock rate to resolve I/O bottleneck problem. The logic and spice simulation results of the proposed architecture are presented. The performances of the proposed architecture are evaluated and compared with other architectures. Finally, the chip layout is shown.