• Journal of Power Electronics
• /
• v.12 no.2
• /
• pp.317-325
• /
• 2012

Resonant immittance converter (RIC) topologies can transform a current source into a voltage source (Type-I RICs) and vice versa (Type-II RICs), thereby making them suitable for many power electronics applications. RICs are operated at a fixed frequency where the resonant immittance network (RIN) exhibits immittance conversion characteristics. It is observed that the low-frequency response of Type-II RINs is relatively flat and that the state variables associated with Type-II RINs affect the response only at the high frequencies in the vicinity of the switching frequency. The overall response of a Type-II RIC is thus dominated by the filter response, which is particularly important for the controller design. Therefore, an approximate equivalent circuit model and a small-signal model of Type-II RICs are proposed in this paper, neglecting the high-frequency response of Type-II RINs. While the proposed models greatly simplify and speed-up the analysis, it adequately predicts the open-loop transient and small-signal ac behavior of Type-II RICs. The validity of the proposed models is confirmed by comparisons of their results with those obtained from a cycle-by-cycle simulation and with an experimental prototype.

• Journal of electromagnetic engineering and science
• /
• v.3 no.2
• /
• pp.86-90
• /
• 2003

A flat conversion loss in microwave mixer is hard to achieve if integrating with an image rejection filter(IRF). This is due to the change of termination condition with respect to the LO and IF frequency at RF port where the filter has 50 ohm termination property only in the RF band. This paper describes a flatness maintenance in the down mixer concerning a diode matching condition as well as an electrical length of embedding line at RF port. The implemented single balance diode mixer is suitable for a 23 ㎓ European Terrestrial Radio. RF, LO and fixed IF frequency chosen in this paper are 21.2∼22.4 ㎓, 22.4∼23.6 ㎓ and 1.2 ㎓, respectively. The measured results show a conversion loss of 8.5 ㏈, flatness of 1.2 ㏈ p-p, input P1㏈ of 7㏈m, IIP3 of 15.42 ㏈m with nominal LO power level of 10㏈m. The return loss of RF and LO port are less than - 15 ㏈ and - 12 ㏈, respectively and IF port is less than - 6 ㏈. LO/RF and LO/IF isolation are 18 ㏈ and 50 ㏈, respectively. This approach would be a helpful reference for designing up/down converter possessing a filtering element.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.12
• /
• pp.56-62
• /
• 2013

We present a rectifier for wireless power transmission using multiplier configuration in layout for MOSFETs which works at 13.56 MHz, designed to fit in CMOS process where conventionally used diodes are replaced with the cross-coupled MOSFETs. Full bridge rectifier structure without comparators is employed to reduce current consumption and to be working up to higher frequency. Multiplier configuration designed in layout reduces time delay originated from parasitic series resistance and shunt capacitance at each finger due to long connecting layout, leading to fast transition from on-state to off-state cross-coupled circuit structure and vice versa. The power conversion efficiency is significantly increased due to this fast transition time. The rectifier is fabricated in $0.11{\mu}m$ CMOS process, RF to DC power conversion efficiency is measured as 86.4% at the peak, and this good efficiency is maintained up to 600 MHz, which is, to our best knowledge, the highest frequency based on cross-coupled configuration.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.18 no.1 s.116
• /
• pp.15-23
• /
• 2007

A simple six-port direct conversion QPSK receiver which is made up of a six-port phase correlator, a signal power detector, and I/Q channel signal de-modulator is designed and implemented in this paper. The output phase signals of six-port phase correlator are also analysed. On the basis of $90^{\circ}C$ phase relation among the six-port phase correlator output signals, the QPSK de-modulation circuit is designed by a simple circuit. The six-port phase correlator is made up of $90^{\circ}$ hybrid branch line and power detector. The six-port phase correlator, which is designed in frequency range of 11.7 to 12.0 GHz, gets the phase error characteristics less than $5^{\circ}$. By considering matching network and amplitude balance in the designed fiequency range, the designed six-port direct conversion QPSK receiver demodulates the I and Q signals with performance less than $5^{\circ}$ phase error.

• Current Optics and Photonics
• /
• v.7 no.4
• /
• pp.378-386
• /
• 2023

A wideband instantaneous frequency measurement (IFM) system is been proposed, designed and analyzed. Phase modulation to intensity modulation conversion is implemented based on the stimulated Brillouin scattering (SBS) effect, and the microwave frequency can be measured by detecting the change in output power. Theoretical analysis shows that the frequency measurement range can be extended to 4f_b by adjusting the two sweeping signals of the phase modulators with a difference of 2f_b. The IFM system is set up using VPI transmission maker software and the performances are simulated and analyzed. The simulation results show that the measurement range is 0.5-45.96 GHz with a maximum measurement error of less than 9.9 MHz. The proposed IFM system has a wider measurement range than the existing SBS-based IFM system.

• Proceedings of the KIEE Conference
• /
• 1988.11a
• /
• pp.283-286
• /
• 1988

This paper describes the PWM cycloconverter which can provide step-up ac-ac direct conversion in a wide output frequency range. With input reactor and output capacitor. the input and output ports are exchanged. And sine PWM scheme is applied to the converter. To analyze the converter operation the state equations are derived using dq transformation. Simulated results show that both the output voltage and frequency can be controlled by adjusting the modulating functions.

• Proceedings of the IEEK Conference
• /
• 2002.06e
• /
• pp.207-210
• /
• 2002

This paper describes a design of multiple-mode single-output DC/DC converter which can be used in both up and down conversion. Proposed up/down converter does not produce a negative voltage which is generated in conventional buck-boost type converter. Three types of operation mode(up/down/bypass) are controlled by the input voltage sense and command signals of target output voltage. PFM(pulse frequency modulation) control is adopted and modified for fast tracking and for precise output voltage level with an aid of output voltage sense. Designed DC/DC converter has the performance of less than 5 % ripple and higher than 80 % efficiency. Chip area is 3.50 mm ${\times}$ 2.05 mm with standard 0.35 $\mu\textrm{m}$ CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.7A
• /
• pp.794-806
• /
• 2004

This paper deals with correction of frequency offset and analysis of quantization angle noise in the IEEE 802.1la OFDM system. The rotation phase per symbol due to the carrier frequency offset is estimated from auto-correlation of the short Preambles, which are over-sampled for the reduction of noise in OFDM signals. The pilot signals are introduced to estimate the rotation phase per OFDM symbol due to estimation error of the carrier frequency offset and the sampling frequency onset. During the estimation and correction of the frequency onsets, a CORDIC processor and a look-up table are used for the conversion between a rotation phase and its complex number. Being calculated by a limited number of bits in the CORDIC processor and the look-up table, the rotation phase and its complex number have quantization angle errors. The quantization errors are analyzed as SNR (signal to noise ratio) due to the quantization bit numbers. The minimum bit number is suggested to meet the specification of IEEE 802.1la properly. Finally, the quantization errors are evaluated through simulations on number of quantization bits and SNR of received signals.

• Journal of the Korea Society of Computer and Information
• /
• v.7 no.4
• /
• pp.115-120
• /
• 2002

This paper presents the implementation of IS-95 CDMA signal processor, baseband and Intermediate Frequency(IF) digital converter using Field Programmable Gate Array(FPGA) and ADC/DAC and frequency up/down converter IS-95 CDMA channel processor is generated the pilot channel signal with short PN code and Walsh-code generator. The digital If is composed of FPGA. digital transmit/receive signal processor and high speed analog-to-digital converter(ADC) and digital-to-analog converter(DAC). The frequency up/down converter consisted of filter, mixer, digital attenuator and PLL is analog conversion between intermediate frequency(IF) and baseband. This implemented system can be deployed in the IS-95 CDMA base station device etc.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.24 no.3
• /
• pp.20-26
• /
• 2010

In ultrashort-pulse reflectometry (USPR), a chirped waveform transformed from the USPR source impulse signal via waveguide makes it possible to employ millimeter-wave mixers for the frequency up-conversion process. Consequently, the frequency bandwidth of the USPR system is sufficiently wide to cover a large portion of the electron density profile of the plasma. Some physical aspects of the chirped waveform, such as maximum amplitude and length, are critical factors to determine the performance of the system. In this paper, the propagation of the USPR impulse signal through a rectangular waveguide is numerically studied to derive the chirped waveform using the impulse response of the waveguide. The results of numerical computation show that the chirped waveform significantly depends on the waveguide cutoff frequency as well as the waveguide length.