• Journal of information and communication convergence engineering
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• v.6 no.2
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• pp.177-181
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• 2008

The more improved the Internet and the information technology, the stronger cryptographic system is required which can satisfy the information security on the platform of personal hand-held devices or smart card system. This paper introduces a case study of designing an elliptic curve cryptographic processor of a high performance that can be suitably used in a wireless communicating device or in an embedded system. To design an efficient cryptographic system, we first analyzed the operation hierarchy of the elliptic curve cryptographic system and then implemented the system by adopting a serial cell multiplier and modified Euclid divider. Simulation result shows that the system was correctly designed and it can compute thousands of operations per a second. The operating frequency used in simulation is about 66MHz and gate counts are approximately 229,284.

• Journal of information and communication convergence engineering
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• v.7 no.4
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• pp.516-520
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• 2009

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyzed the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture prototype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the RSA processor.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.399-400
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• 2008

This paper presents a new architecture of unified IP/IT/IQ/MC circuit for H.264 decoder based on operation sharing and efficient scheduling. The resultant circuit based on the proposed architecture uses only 12 adders and 1 multiplier. We further reduced the circuit size by sharing buffers. Our circuit consists of 47,810 gates and operates at the maximum operating frequency of 117MHz with 130nm standard cells.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.6
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• pp.145-152
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• 1998

This paper presents an optimum design of a rotor-bearing spindle system for a ultra centrifuge (80,000 RPM) supported by ball bearings with nonlinear stiffness characteristics. To obtain the nonlinear bearing stiffnesses, a ball bearing is modeled in five degrees of freedom and is analyzed quasi-statically. The dynamic behaviors of the nonlinear rotor-bearing system are analyzed by using a transfer-matrix method iteratively. For optimization. we use the cost function that simultaneously minimizes the weight of a rotor and maximizes the separation margins to yield the critical speeds as far from the operating speed as possible. Augmented Lagrange Multiplier (ALM) method is employed for the nonlinear optimization problem. The result shows that the rotor-bearing spindle system is optimized to obtain 9.5％ weight reduction and 21％ separation margin.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.4
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• pp.513-519
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• 1990

In order to realize an efficient and stable X-band harmonic generator, a 100 MHz frequency multiplier, an impulse generator using SRD(Step Recovery Diode) module, and a narrow-band bandpass waveguide filter have been designed and tested. By properly combining these devices an X-band harmonic generator has been realized. The output power of the harmonic generator was measured to be -1.5 dBm at 9 GHz which is the 90th harmonic of the 100MHz input. The power fluctuation of the harmonic generator due to temperature variation was observed to the about 0.15 dB during 24 hours of 4\ulcorner temperature variation.

• ETRI Journal
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• v.32 no.1
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• pp.1-10
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• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

• Journal of the Optical Society of Korea
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• v.8 no.1
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• pp.29-33
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• 2004

We propose and demonstrate a novel optical pulse multiplier applicable to OTDM (Optical Time Division Multiplexing) systems using cascaded long-period fiber gratings. We have exploited the fact that each mode in a fiber has a different propagation constant to obtain time delays among optical pulses. The proposed scheme could realize high-frequency optical pulse multiplication for optical short pulse trains. We have successfully implemented two, four, and eight times multiplications with the maximum repetition rate of 416.7 ㎓. The obtained pulse delays are well matched with the simulated ones.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.6A
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• pp.855-861
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• 2000

This paper concerns a development of LQ-servo PI controller design on the basis of time-domain approach. The motivation is because the previous design techniques developed on the frequency-domain is not well suited meet the time-domain design specifications. Our development techniques used in this paper is base on the convex optimization methods including Lagrange multiplier, dual concept, semidefinite programming.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2005.11a
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• pp.830-833
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• 2005

SDM(Structural Dynamics Modification) is to improve dynamic characteristics of a structure, more specifically of a base structure, by adding or deleting auxiliary(modifying) structures. In this paper, I will focus on the optimal layout of the stiffeners which are attached to the plate to maximize 1st natural frequency. Recently, a new topology method was proposed by yamazaki. He uses growing and branching tree model. I modified the growing and branching tree model. The method is designated modified tree model. To expand the layout of stiffeners, I will consider non-matching problem. The problem is solved by using local lagrange multiplier without the mesh regeneration. Moreover The CMS(Component mode synthesis) method is employed to reduce the computing time of eigen reanalysis using reduced componet models.

• Journal of electromagnetic engineering and science
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• v.18 no.3
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• pp.188-198
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• 2018

In this study, we propose an approach for the design and satisfy the requirements of the fabrication of a small, lightweight, reliable, and stable ultra-wideband receiver for millimeter-wave bands and the contents of the approach. In this paper, we designed and fabricated a stable receiver with having low noise figure, flat gain characteristics, and low noise characteristics, suitable for millimeter-wave bands. The method uses the chip-and-wire process for the assembly and operation of a bare MMIC device. In order to compensate for the mismatch between the components used in the receiver, an amplifier, mixer, multiplier, and filter suitable for wideband frequency characteristics were designed and applied to the receiver. To improve the low frequency and narrow bandwidth of existing products, mathematical modeling of the wideband receiver was performed and based on this spurious signals generated from complex local oscillation signals were designed so as not to affect the RF path. In the ultra-wideband receiver, the gain was between 22.2 dB and 28.5 dB at Band A (input frequency, 18-26 GHz) with a flatness of approximately 6.3 dB, while the gain was between 21.9 dB and 26.0 dB at Band B (input frequency, 26-40 GHz) with a flatness of approximately 4.1 dB. The measured value of the noise figure at Band A was 7.92 dB and the maximum value of noise figure, measured at Band B was 8.58 dB. The leakage signal of the local oscillator (LO) was -97.3 dBm and -90 dBm at the 33 GHz and 44 GHz path, respectively. Measurement was made at the 15 GHz IF output of band A (LO, 33 GHz) and the suppression characteristic obtained through the measurement was approximately 30 dBc.