• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.141-148
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• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

• Journal of KSNVE
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• v.6 no.6
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• pp.771-779
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• 1996

In this paper, double Fourier sine series is used as a modal displacement functions of a rectangular plate and applied to the free vibration analysis of a rectangular plate under various boundary conditions. The method of stationary potential energy is used to obtain the modal displacements of a plate. To enhance the flexibility of the double Fourier sine series, Lagrangian multipliers are utilized to match the geometric boundary conditions, and Stokes' transformation is used to handle the displacements that are not satisfied by the double Fourier sine series. The frequency parameters and mode shapes obtained by the present method are compared with those obtained by MSC/NASTRAN and other analysis.

• Journal of information and communication convergence engineering
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• v.11 no.3
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• pp.190-198
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• 2013

Recently, one of the most vital advancement in the field of finance is high-performance trading using field-programmable gate array (FPGA). The objective of this paper is to design high-performance Black Scholes option trading system on an FPGA. We implemented an efficient Black Scholes Call Option System IP on an FPGA. The IP may perform 180 million transactions per second after initial latency of 208 clock cycles. The implementation requires the 64-bit IEEE double-precision floatingpoint adder, multiplier, exponent, logarithm, division, and square root IPs. Our experimental results show that the design is highly efficient in terms of frequency and resource utilization, with the maximum frequency of 179 MHz on Altera Stratix V.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2001.11b
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• pp.719-724
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• 2001

The study on reducing vehicle noise and vibration has gained much attention to ensure the comfortability as well as the safety. These days. in this paper, we applied Statistical Energy Analysis(SEA) to characterize the tire assembly, which is useful analytical tool for mid- and high-frequency range. First, the SEA tire model was developed by dividing the tire and the wheel into several subsystems. The material properties were estimated experimentally. Finally. the SEA model was validated by comparing the estimated and the measured. In addition, we investigated the energy level and the energy transfering paths through the tire assembly in different frequency region.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.35-46
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• 1999

A derotator VLSI which compensates for the frequency and phase errors of a received signal in digital communication systems was developed employing a CORDIC algorithm. The CORDIC circuit directly rotates the input signal according to the phase error information, thus is much simpler than the conventional derotator architecture which consists of a DDFS (Direct Digital Frequency Synthesizer) and a complex multiplier. Since a derotator needs only small phase error accumulation, a fast direction sequence generation method which exploits the linearity of the arctangent function in small angles is utilized in order to enhance the operating speed. The chip was designed and implemented using a $0.6\mu\textrm{m}$ triple metal CMOS process by the full custom layout method. The whole chip size is $6.8\textrm{mm}^2$ and the maximum operating frequency is 25 MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1137-1140
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• 2011

In this paper, the optimal condition for efficient active frequency multipliers is analyzed. This analysis is based on the effects from transistor nonlinear coefficients, harmonic impedances, and output parasitic components. From the analysis, normalized harmonic power is estimated with the clipping condition of a commercial transistor, and the condition for high conversion efficiency is suggested. From the analysis, a class-F frequency tripler was implemented for the output at 2.475 GHz, showing the maximum efficiency of 22.9 % and the maximum conversion gain of 9.5 dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.94-104
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• 2008

In this paper, we propose a new architecture of multiplier-and-accumulator (MAC) for high speed multiplication and accumulation arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator which has the largest delay in MAC was removed and its function was included into CSA, the overall performance becomes to be elevated. The proposed CSA tree uses 1's complement-based radix-2 modified booth algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of operands. The CSA propagates the carries by the least significant bits of the partial products and generates the least significant bits in advance for decreasing the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits not the output of the final adder for improving the performance by optimizing the efficiency of pipeline scheme. The proposed architecture was synthesized with $250{\mu}m,\;180{\mu}m,\;130{\mu}m$ and 90nm standard CMOS library after designing it. We analyzed the results such as hardware resource, delay, and pipeline which are based on the theoretical and experimental estimation. We used Sakurai's alpha power low for the delay modeling. The proposed MAC has the superior properties to the standard design in many ways and its performance is twice as much than the previous research in the similar clock frequency.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.1
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• pp.85-91
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• 2012

In this paper, we implemented a Ka-band frequency synthesizer for millimeter wave seeker. we designed for high frequency resolution and frequency hopping response time in the digital synthesis method which uses DDS(Direct Digital Synthesizer). but frequency bandwidth was limited low frequency because DDS output frequency was limited 1/2 by system clock. thus, frequency synthesizer was converted to Ka-band using the frequency multiplier ${\times}4$ and local oscillator. proposed frequency synthesizer was bandwidth 500MHz, frequency switching time was $0.7{\mu}s$, spurious level was suppressed below -52dBc. phase noise was -99dBc/Hz at offset 100kHz and flatness was ${\pm}1dB$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.2A
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• pp.213-219
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• 2007

In this paper, A novel structure of frequency doubler using Phase Delay line and $90^{\circ}$ Hybrid coupler at harmonic output have been designed and implemented to improve suppression. Proposed structure of frequency doubler improve output. coupling and fundamental suppression. Active frequency doubler with band from $2.13{\sim}2.15GHz\;to\;4.26{\sim}4.3GHz$ was designed and fabricated with 10dBm input power, 0.79dB conversion gain and -55.54dBc suppression at fundamental frequency, -44.76dBc suppression at third harmonic frequency 6.42GHz and -39.18dBc suppression at fourth harmonic frequency 8.56GHz.

• Journal of international Conference on Electrical Machines and Systems
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• v.3 no.2
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• pp.132-138
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• 2014

We investigated the harmonic voltages generated by a synchronous machine adding d-axis and q-axis harmonic field windings to reduce the harmonics in a power line. First, electronic circuits such as a frequency multiplier, band-pass filter, and phase shifter were newly designed and made to carry out the experiment. Next, an experimental circuit, for which an AC voltage of frequency 6f synchronized to the power line voltage of frequency f could be obtained, was constructed to examine the generation of harmonic voltage in more detail. Finally, an experiment involving the generation of harmonic voltage was performed using an experimental synchronous generator with harmonic windings in the d-axis and q-axis. In this paper, the power spectrum and the waveforms of the harmonic voltages in the armature winding are presented. Moreover, the values calculated from theoretical expressions of harmonic voltages in armature winding are compared with the values obtained by the experiment.