• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.28-33
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• 2006

An integrated 3.125Gbps clock and data recovery (CDR) circuit is presented. The circuit does not need a reference clock. It has a phase and frequency detector (PFD), which incorporates a bang-bang type 4X oversampling PD and a rotational frequency detector (FD). It also has a ring oscillator type VCO with four delay stages and three zero-offset charge pumps. With a proposed PD and m, the tracking range of 24% can be achieved. Experimental results show that the circuit is capable of recovering clock and data at rates of 3.125Gbps with 0.18 um CMOS technology. The measured recovered clock jitter (p-p) is about 14ps. The CDR has 1.8volt single power supply. The power dissipation is about 140mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.130-134
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• 2008

This paper presents a clock and data recovery(CDR) using a quarter-rate technique. The proposed CDR helps reduce the VCO frequency and is thus advantageous for high speed application. It can achieve a low jitter operation and extend the pull-in range without a reference clock. The CDR consists of a quarter-rate bang-bang type phase detector(PD) quarter-rate frequency detector(QRFD), two charge pumps circuits(CPs), low pass filter(LPF) and a ring voltage controlled oscillator(VCO). The Proposed CDR has been fabricated in a standard $0.18{\mu}m$ 1P6M CMOS technology. It occupies an active area $1{\times}1mm^2$ and consumes 98 mW from a single 1.8 V supply.

• The Journal of the Acoustical Society of Korea
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• v.28 no.4
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• pp.401-407
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• 2009

In this paper, we propose a novel method for the cross-correlation based double-talk detection (DTD), which employing the Gaussian Mixture Model (GMM) in the frequency domain. The proposed algorithm transforms the cross correlation coefficient used in the time domain into 16 channels in the frequency domain using the discrete fourier transform (DFT). The channels are then selected into seven feature vectors for GMM and we identify three different regions such as far-end, double-talk and near-end speech using the likelihood comparison based on those feature vectors. The presented DTD algorithm detects efficiently the double-talk regions without Voice Activity Detector which has been used in conventional cross correlation based double-talk detection. The performance of the proposed algorithm is evaluated under various conditions and yields better results compared with the conventional schemes. especially, show the robustness against detection errors resulting from the background noises or echo path change which one of the key issues in practical DTD.

• 전기의세계
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• v.22 no.1
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• pp.35-41
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• 1973

An automatic point traffic control method is recommended for more idealistic traffic flow over coarse road netowrks. The automatic control apparatus recommended, consists of a transceiver, amplifier, digital-to-analog converter, signal light controller for emergency and steady state, and digital counter as monitor. The transmitter sends a signal to the target vy means of Microwave-FM-CW and a diode detector picks up the echo signal. Thus the operation of the entire system will be carried out through an open loop state. Some factors necessary for an ideal detector system are rapid response, longevity and stability. An analytical method of the Doppler effect substitutes the conventional frequency deviation into the amplitude of detector output. The changing rate of amplitude is proportional to the voltage of the detector output. Some induced formula from Maxwell's radiation field theory ensures this new method, and, new method, and proves the fact with an experimental data presentation. Stability depends upon Klystron as an oscillator and a diode as a detector. the transceiver installation affects on the response and sensitivity of the system. In accordance with the detector output, several targets are easily classified by amplitudes on the scope. The traffic flow, i.e., target movement which is analyzed by the amplitude method, is shown through the scope and indicates it on the digital counter. The best efficiency for the amplitude analysis can be attained through use of an antenna having the highest sensitivity.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.368-371
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• 2000

The PLL(Phase-Locked Loop) techniques re employed to make the switching frequency of a resonant inverter follow the resonant frequency which may vary due to the load variations during operation. The conventional design guide of PLL is not suitable in these case since the inverter characteristics are not considered. In this paper the phase characteristics of a resonant inverter is analysed and added to the closed loop. And the design of PLL with digital phase detector is illustrated for the output frequency to track the resonant frequency of the inverter.

• MALSORI
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• no.48
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• pp.155-173
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• 2003

This paper proposes a noise reduction-based speech detection method under telephone channel environments. We adopt the AURORA front-end noise reduction algorithm based on the two-stage mel-warped Wiener filter approach as a preprocessor for the frequency domain speech detector. The speech detector utilizes mel filter-bank based useful band energies as its feature parameters. The preprocessor firstly removes the adverse noise components on the incoming noisy speech signals and the speech detector at the next stage detects proper speech regions for the noise-reduced speech signals. Experimental results show that the proposed noise reduction-based speech detection method is very effective in improving not only the performance of the speech detector but also that of the subsequent speech recognizer.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.394-397
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• 2002

A design study of phase detectors for the 2.5 Gb/s CDR circuit using a standard 0.18-${\mu}{\textrm}{m}$ CMOS process has been performed. The targeted CDR is based on the phase-locked loop and thus it consists of a phase detector, a charge pump, a LPF, and a VCO. For high frequency operation of 2.5 Gb/s, phase detector and charge pump, which accurately compare phase errors to reduce clock jitter, are critical for designing a reliable CDR circuit. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.706-711
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• 2014

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1945-1947
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• 2000

In this paper, we manufactured the detector which is detecting the periodical distribution of arrival time about pulsed leaky noise. The frequency range were analyzed optimally pulsed leaky noise in detector design. With results we can make the detector for leaky noise from the bad insulator.

• Proceedings of the KSR Conference
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• 2005.11a
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• pp.777-782
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• 2005

In this paper, we designed and fabricated a partial discharge (PD) detector to diagnose the soundness of CNCV cables by analyzing PD pulses and to predict discharge locations. The PD detector is consisted of a coupling network with a discharge free capacitor and a detection impedance, a voltage follower and a low noise amplifier. Lower cut-off frequency of the detector is adjusted at 175kHz to block AC voltage and to pass discharge pulse only. The discharge location could be obtained by the time of arrival method using travelling wave propagation theory. In a laboratory test on an eighty meter CV cable, we could position the discharge location within a two meter error.