• Journal of Electrical Engineering and Technology
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• 제13권2호
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• pp.875-880
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• 2018

This paper proposes a novel combined compensation structure in the infrared receiver chip. For the infrared communication chip, the current-voltage (I-V) convert circuit is crucial and important. The circuit is composed by the transimpedance amplifier (TIA) and the combined compensation structures. The TIA converts the incited photons into photocurrent. In order to amplify the photocurrent and avoid the saturation, the TIA uses the combined compensation circuit. This novel compensation structure has the low frequency compensation and high frequency compensation circuit. The low frequency compensation circuit rejects the low frequency photocurrent in the ambient light preventing the saturation. The high frequency compensation circuit raises the high frequency input impedance preserving the sensitivity to the signal of interest. This circuit was implemented in a $0.6{\mu}m$ BiCMOS process. Simulation of the proposed circuit is carried out in the Cadence software, with the 3V power supply, it achieves a low frequency photocurrent rejection and the gain keeps 109dB ranging from 10nA to $300{\mu}A$. The test result fits the simulation and all the results exploit the validity of the circuit.

• 센서학회지
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• 제21권3호
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• pp.235-239
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• 2012

This paper presents frequency response compensation technique, and a self-oscillation circuit for capacitive microresonator with the compensation technique using programmable capacitor array, to compensate for the frequency response distorted by parasitic capacitances, and to obtain stable oscillation condition. The parasitic capacitances between the actuation input port and capacitive output port distort the frequency response of the microresonator. The distorted non-ideal frequency response can be compensated using two programmable capacitor arrays, which are connected between anti-phased actuation input port and capacitive output port. The simulation model includes the whole microresonator system, which consists of mechanical structure, transimpedance amplifier with automatic gain control, actuation driver and compensation circuit. The compensation operation and oscillation output of the system is verified with the simulation results.

• 한국군사과학기술학회지
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• 제23권3호
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• pp.213-220
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• 2020

This paper proposes a method on the performance analysis of pulse repetition frequency jitter compensation for generating Doppler profile. Exact phase compensation of each pulse is required to obtain Doppler profiles under pulse repetition frequency jitter. Three parameters such as velocity, pulse repetition frequency, and carrier frequency are examined to cause errors when conducting the pulse repetition frequency jitter compensation, then assuming well-focused Doppler profiles reflect well-conducted pulse repetition frequency jitter compensation, the proposed method in this paper utilizes the contrast to measure how well Doppler profile is generated. These are validated by electromagnetic computation data and computer simulation. Then, it is concluded which parameter is important on the performance analysis of pulse repetition frequency jitter compensation by using the contrast.

• Journal of electromagnetic engineering and science
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• 제3권2호
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• pp.79-85
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• 2003

In this paper, we investigated the degree of compensation for distorted optical pulse of wavelength division multiplexed(WDM) channel with initial frequency chirp generated in optical transmitter. The WDM channel signal distortion is due to chromatic dispersion, self phase modulation(SPM) and cross phase modulation(XPM) in fiber. The considered system is 3 ${\times}$ 40 Gbps intensity modulation direct detection(IM/DD) WDM transmission systems, which adopted mid-span spectral inversion(MSSI) as compensation method. We confirmed that the effect of initial frequency chirp on compensation for signal distortion due to a SPM is gradually decreased as a dispersion coefficient of fiber becomes gradually small. But, in the aspect of a compensation for signal distortion due to both SPM and XPM, the effect of initial frequency chirp on compensation is gradually decreased as a dispersion coefficient of fiber becomes gradually large.

• Journal of Power Electronics
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• 제10권6호
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• pp.749-761
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• 2010

The switching frequency of a power device is a very important parameter in the design of a parallel active power filter (PAPF), but so far, very little discussion has been conducted on it in a quantitative manner in previous publications. In this paper, an extensive analysis on the effects of the switching frequency on the performance of a PAPF is made, and a specification of the switching frequency values with different compensation results is presented. A first-order inertia element and a second-order oscillation element are considered as approximate models of a PAPF, respectively. The compensation characteristic for each order of harmonic current is obtained at different switching frequencies. Then, the THDs of each model for the system loads of a rectifier with resistance and inductance loads are proposed. The compensation results of a PAPF controlled as a first-order inertia element are better than those of a PAPF controlled as a second-order oscillation element. With two types of system loads which are rectifier with resistance and inductance loads and rectifier with resistance, inductance and capacitance loads, the THDs of the source current after compensation are presented with different switching frequencies. The compensation characteristics for the most widely used digital control system are investigated. The situation with an analog control is the theoretical characteristic and it is the best situation. The compensation characteristic of the digital control is worse than the compensation characteristic of the theoretical characteristic. Based on these analyses, the specifications of compensation characteristics with different switching frequencies are quite straightforward. Finally, a practical design example is studied to verify the application.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.201-202
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• 2008

In this paper, an efficient frequency offset compensation design for OFDM(Orthogonal Frequency Division Multiplexing) is proposed. The conventional CORDIC(COordinate Rotation Digital Computer) algorithm for frequency offset compensation utilizes CORDIC hardware and complex multiplier. But, proposed structure utilizes only one CORDIC hardware.

• 한국정밀공학회지
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• 제9권1호
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• pp.126-136
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• 1992

In this paper, a simple structured feedback compensation scheme for a electro-hydraulic servo system to keep the response characteristics unchanged regardless of the load variation is proposed. In electro-hydraulic servo system, servovalve is most important control element. But the relation between input corrent and output flowrate of the servovalve has properties as follows; firstly, in spite of constant input current, output flowrate decreases as load pressure increases, secondly, according to frequency response of typical servovalve, the characteristics of gain and phase shift is something like 2'nd order system. Load pressure feedback compensation method has been applied to eliminate the first influence, the second influence has been improved by phase lead compensation method. As a result of above compensation methods, regardless of variation load condition, spring and inertia load, the compensation scheme has been verified to be effective within the range of frequency less than 25Hz by static response and dynamic response in time domain and frequency domain through experiments.

• 전기학회논문지P
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• 제55권1호
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• pp.1-5
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• 2006

In this paper, the frequency estimator and DFT filter gain compensation for UFR(Under Frequency protection Relay) is introduced. Due to the sudden appearance of generator loads or faults in power system, the frequency is supposed to deviate from its nominal value. Because a frequency calculation is based on phase information, it needs sufficient sampling data to figure out a precious frequency. Therefore the frequency measurement for UFR needs excellent qualities such as high speed and precision with low sampling frequency Authors propose the frequency estimator which compares the vector differences and the DFT filter gain compensation which identifies DFT filter error and correct it. Using the frequency estimator and compensation, UFR which has the 0.01[ms] calculation delay and 0.003[Hz] measurement error is implemented with digital processor.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.574-576
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• 2008

Now there are two types Non-contact compensation AC automatic voltage regulator (A.V.R). One is transformer compensation regulator, whose principle is the combination of multiple compensation transformers, do the compensation by turning on and off the connections of the transformer through the multi-full bridge circuit. This method removed the mechanical drive and contacts, which increases the life and the dynamic performance of the A.V.R. However, the compensation is multilevel, and it needs many compensation transformers and switches, the circuit is complex, the compensation precision is low. Another type is PWM switch AC regulator, whose principle is getting the AC voltage from the input, then induce the AC compensation voltage through commutating and high frequency PWM transforming, and phase tracking. Here the compensation is step-less, the compensation precision is high, and the response is fast. But the circuit is complex, and it needs an inverse compensation transformer, which is difficult to realize high-power applications. In this paper, it shows an Automatic Voltage Regulator which use high frequency PWM inverter do compensation. This A.V.R has the function as the custom-power, which make the performance of the power supply in a high level.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.241-246
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.