• Journal of the Korean Solar Energy Society
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• v.38 no.1
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• pp.45-55
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• 2018

Environmentally benign lead-free solder coated ribbon (e. g. SnCu, SnZn, SnBi${\cdots}$) has been intensively studied to interconnect cells without lead mixed ribbon (e. g. SnPb) in the crystalline silicon(c-Si) photovoltaic modules. However, high melting point (> $200^{\circ}C$) of non-lead based solder provokes increased thermo-mechanical stress during its soldering process, which causes early degradation of PV module with it. Hence, we proposed low-temperature conductive paste (CP) based tabbing method for lead-free ribbon. Modules, interconnected by the lead-free solder (SnCu) employing CP approach, exhibits similar output without increased resistivity losses at initial condition, in comparison with traditional high temperature soldering method. Moreover, 400 cycles (2,000 hour) of thermal cycle test reveals that the module integrated by CP approach withstands thermo-mechanical stress. Furthermore, this approach guarantees strong mechanical adhesion (peel strength of ~ 2 N) between cell and lead-free ribbons. Therefore, the CP based tabbing process for lead free ribbons enables to interconnect cells in c-Si PV module, without deteriorating its performance.

• Journal of the Korean Ceramic Society
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• v.32 no.4
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• pp.489-497
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• 1995

The DDS((CH3)2SiCl2)＋H2 gas mixture, where C atoms exist in excess in the molecules, was used for chemical vapor deposition of SiC in order to prevent codeposition of free Si in MTS(Ch3SiCl3)＋H2 system. The deposition rate was more rapid than MTS, however differ from that of MTS, it decreased after shwoing a maximum at 140$0^{\circ}C$. The stoichiometry was highly improved by using the DDS as a precursor, although there exist a little pyrolytic C at 150$0^{\circ}C$. The preferred orientation was (220) in MTS, however, it changed to (111) in DDS. The microstructure of the layer deposited at lower temperature were dense, however it grew coarse with the increase in the temperature.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.436-438
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• 1987

The thermal oxidation recipe has been optimized for very thin (12 nm) capacitor oxide for Mega bit DRAM. The time dependent dielectric breakdown characteristics show that the breakdown voltage and time to breakdown are very high and uniform, indication that our oxide is defect free and suitable for DRAM capacitor dielectric. To our knowledge this is the best oxide quality obtained up tp now around 10 nm.

• Bulletin of the Korean Chemical Society
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• v.21 no.8
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• pp.817-822
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• 2000

Crack-free hard coating siIica films were prepared by sol-gel processfrom twokinds of silicon alkoxide (tetra-ethoxysilane and methyltrimethoxysilane) and two kinds of alcohol (methanol and isopropyl alcohol) with an acid catalyst,acetic acid. A silicate framework of the precursor solution was investigated by infrared spectros-copy (IR) in the process of hydrolysis and condensation. Theextent of the condensation in the intermediates was elucidated by gel permeation chromatography (GPC) and 29Si-NMR spectroscopy. The hard coating films werecharacterized by IR,scanning electron microscope (SEM), thermo gravimetric analyzer (TGA) and dif-ferential scanning calroimeter (DSC). The synthetic condition for the crack-free and transparent silica film for-mation was optimized interms of starting materials for the precursor solution as well as preparation method of the silica film.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.2
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• pp.51-54
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• 2019

The electrodeposition of rhodium (Rh) on silicon substrate at different current conditions were investigated. The cracks were found at high current density during the direct current (DC) plating. The pulse current (PC) plating were applied to avoid the formation of cracks on the deposits. Off time in the pulse plating relieved the residual stress of the Rh deposits and consequently the current conditions for the crack-free Rh deposits were obtained. Optimum pulse current (PC) condition is 5:5 (on:off) for the crack-free Rh electroplating.

• Proceedings of the Korean Institute of Building Construction Conference
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• 2023.05a
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• pp.31-32
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• 2023

Recently, with the digitalization of the construction industry, free-form building construction technology is developing. However, the technology for manufacturing free-form concrete panels is still insufficient. In this study, the surface error of the FCP according to the thickness of the lower silicon plate, which is a component of the existing lower multi-point press, was analyzed in order to manufacture a precise FCP. As a result of the analysis, it was found that the thinner the thickness, the larger the error value. These results can be used as a basis for existing research and are expected to be used for research on high-quality FCP manufacturing technology.

• Journal of the Korean Ceramic Society
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• v.38 no.6
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• pp.531-536
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• 2001

SiCl$_4$/CH$_4$/H$_2$계를 사용한 플라즈마 화학증착법(PECVD)으로 실리콘(100) 기판 위에 3C-SiC막을 117$0^{\circ}C$~1335$^{\circ}C$의 온도범위에서 증착하였다. 증착온도, 유입가스비, R$_{x}$ [=CH$_4$/(CH$_4$+H$_2$)], 그리고 r.f. power를 변화시켜 증착막의 결정성에 대해 검토하였다. Thermal CVD에 비해 PECVD법은 박막의 증착속도를 향상시켰다. 증착된 3C-SiC은 (111) 면으로 최대의 우선배향성을 지님을 알 수 있었다. 실리콘 기판 위의 3C-SiC막의 결정성은 R$_{x}$값에 의존하였으며, R$_{x}$가 감소할수록 결정성이 더욱 향상되었다. Free Si가 3C-SiC막과 함께 증착되었으나, 증착온도와 r.f power가 증가함에 따라 free Si의 함량은 감소하였다. 증착온도 127$0^{\circ}C$, 유입가스비 R$_{x}$=0.04, r.f. power가 60W에서 비교적 결정성을 가진 3C-SiC막을 얻을 수 있었다.

• Korean Journal of Optics and Photonics
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• v.9 no.3
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• pp.156-161
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• 1998

We developed aerosol flame deposition method and made stress-free Pyrex-based optical waveguide on silicon substrate using this method. Zr is doped to control the refractive index of Pyrex waveguide layers. The refractive index of the film changes from 1.460 to 1.475 as the content of Zr changes from 0 to 3 wt%. Er is doped to see the possibility of applying this Pyrex waveguide as PLC-type (Planar Lightwave Circuit) optical amplifier. The refractive index of the film changes from 1.460 to 1.465 as the content of Zr changes from 0 to 1 wt%. Light launching using a prism coupler to the fabricated waveguide showed good quality for application to PLC. The polarization dependence of refractive-index of the Pyrex film is measured to be less than $2{\times}10^{-4}$.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.4
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• pp.210-214
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• 2002

The crystallization behavior of amorphous silicon (a-Si) film was investigated by using Cu-field aided lateral crystallization (Cu-FALC) process below $450^{\circ}C$. The lateral crystallization was induced from the Cu deposited region outside of pattern toward the Cu-free region inside of the pattern by applying an electric field during heat treatment. As expected, the lateral crystallization toward Cu-free region proceeded from negative toward positive electrode side. The occurrence of Cu-FALC phenomenon was interpreted in terms of dominant diffusing species in the reaction between Cu and Si. Even at the annealing temperature of $350^{\circ}C$, the large dendrite-shaped branches were formed in the crystallized region and the polarity in the lateral crystallization was clearly observed. Consequently, we could successfully crystallize the a-Si at the temperature as low as $350^{\circ}C$ by an electric field of 30 V/cm with fast crystallization velocity of 12 $\mu$m/h.