• E2M - 전기 전자와 첨단 소재
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• 제9권7호
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• pp.708-718
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• 1996

The microstructure and electrical properties of the nonlinear ZnO varistor with A1$_{2}$ $O_{3}$ additions is investigated. The variation of nonlinear behavior with A1$_{2}$ $O_{3}$ additions is indicated from J-E and C-V measurement to be a result of the change of the interface defects density $N_{t}$ at the grain boundaries and the donor concentration $N_{d}$ in the ZnO grains. The optimum composition which has the nonlinear coefficients of -57 was observed in the sample with 0.005wt% A1$_{2}$ $O_{3}$ additions. The conduction mechanism at the pre-breakdown region is consistent with a Schottky thermal emission process obeying a relation given by $J^{\var}$exp[-(.psi.-.betha. $E^{1}$2/)kT] and the conduction process at the breakdown region follows a Fowler-Nordheim tunneling mechanism of the form $J^{\var}$exp(-.gamma./E).

• 한국전기전자재료학회논문지
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• 제22권11호
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• pp.980-986
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• 2009

In a triple-layered structure of ITO/N,N'-diph enyl-N,N'bis(3-methylphenyl)-1,1' - biphenyl-4,4'-diamine(TPD)/tris(8-hydroxyquinoline)aluminum($Alq_3$)/(2,9-Dimethyl-4,7-diphenyl-1,10-phenanthroline(BCP)/Al device, we have studied the electrical and optical characteristics of organic light-emitting diodes(OLEDs) depending on the deposition condition of BCP layer. Several different sizes of holes on boat and several different deposition rates were employed in evaporating the organic materials. And then, electrical properties of the organic light-emitting diodes were measured and the performance of the devices was analyzed. It was found that the hole-size of crucible boat and the evaporation rate affect on the surface roughness of BCP layer as well as the performance of the device. When the hole-size of crucible boat and the deposition rate of BCP are 1.2 mm and $1.0\;{\AA}/s$, respectively, average surface roughness of BCP layer is lower and the efficiency of the device is higher than the ones made with other conditions. From the analysis of current density-luminance-voltage characteristics of a triple layered device, we divided the conductive mechanism by four region according to applied voltage. So we have obtained a coefficient of ${\beta}_{ST}$ in schottky region is $3.85{\times}10^{-24}$, a coefficient of ${\beta}_{PF}$ in Poole-Frenkel region is $7.35{\times}10^{-24}$, and a potential barrier of ${\phi}_{FN}$ in Fower-Nordheim region is 0.39 eV.

• 한국재료학회지
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• 제2권4호
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• pp.285-292
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• 1992

Si(100) 웨이퍼를 사용하여 RTP 장비에서 $O_2$와 $N_2$O 분위기에서 8nm의 oxynitride를 제조 하였다. 기존의 로(furnace) 열산화막과 비교해서 oxynitride는 I-V, TDDB 특성이 우수하였고, flat-band voltage shift도 적었으며 $BF_2이온$ 주입에 의한 붕소 투과 억제 특성도 우수하다. 유전상수는 oxynitride가 열산화막에 비해서 크다. Oxynitride는 순수한 Si$O_2$유사하게 V 〉${\varphi}_0$ 구간에서 Fowler-Nordheim 터널링 특성을 나타낸다. SIMS, AES, 그리고 XPS 분석 결과 질소 pile-up이 Si$O_2$/Si 계면에서 나타나고, 이것은 oxynitride 산화막 특성 향상과 깊은 관련이 있다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.729-732
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• 2001

In this study, the effect of oxygen partial pressure on the electrical properties of vanadium oxide(VO$_{x}$) thin films were investigated. The thin films were prepared by r.f. magnetron sputtering from V$_2$O$_{5}$ target in a gas mixture of argon and oxygen. The oxygen partial pressure ratio is changed from 0% to 8%. I-V characteristics were distinguished between linear and nonlinear region. In the low field region the conduction is due to Schottky emission, while at high fields it changes to Fowler-Nordheim tunneling type conduction. The conductivity measurements have shown an Arrhenius dependence of the conductivity on the temperature.ure.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.435-438
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• 2003

The effects of oxygen partial pressure and vacuum annealing on the electrical properties of sputtered vanadium oxide($VO_x$) thin films were investigated. The thin films were prepared by r.f. magnetron sputtering from $V_2O_5$ target in a gas mixture of argon and oxygen. The oxygen/(oxygen+argon) partial pressure ratio of 0% and 8% is adopted. Electrical properties of films sputter-deposited under different oxygen gas pressures and in situ annealed in vacuum at $400^{\circ}C$ for 1h and 4h are characterized through electrical conductivity measurements. I-V characteristics were distinguished between linear and nonlinear region. In the low field region the conduction is due to Schottky emission, while at high fields it changes to Fowler-Nordheim tunneling type conduction. The conductivity measurements have shown an Arrhenius dependence of the conductivity on the temperature.

• 한국재료학회지
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• 제4권1호
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• pp.63-74
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• 1994

$SiO_{2}$초박막(ultrathin film)의 두께 조절 용이성, 두께 균일성, 공정 재현성 및 전기적 특성을 향상시키기 위해 실리콘을 $N_{2}O$분위기에서 열산화시켰다. $N_2O$분위기에서 박막 성장시 산화와 동시에 질화가 이루어지기 때문에 전기적 특성의 향상을 가져올 수 있었다. 질화 현상에 의해 형성된 Si-N결합 형성은 습식 식각율과 ESCA분석으로 확인할 수 있었다. $N_2O$분위기에서 성장된 $SiO_{2}$박막은 Fowler-Nordheim(FN)전도 기구를 보여주었으며, 절열파괴 특성과 누설 전류특성 및 산화막의 신뢰성은 건식 산화막에 비해서 우수하였다. 또한 계면 포획밀도는 건식 산화막에 비해 감소하였고, 전하를 주입했을 때 생성되는 계면 준위의 양 또는 크게 감소하였다. 산화막 내부에서의 전하 포획의 양도 감소하였고, 전하를 주입하였을 때 생성되는 전하 포획의 양도 감소하였다. 이와 같은 전기적인 특성의 향상은 산화막 내부에서 약하게 결합하고 있는 Si-O 결합들이 Si-N결합으로의 치환과 스트레스 이완에 의하여 감소하였기 때문이다.

• 대한전자공학회논문지
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• 제26권11호
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• pp.1699-1705
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• 1989

Nitridation of about 300\ulcornerSiO2 filmss thermally grown on Si was performed in NH3 plasm ambient (0.2-2 torr) at 900\ulcornerC-1100\ulcorner for 15-20 minutes. The peoperties of those films have been investigated by analyzing the AES and the SIMS data, and the results of the I-V and the C-V measurements. At the plasma ambient of less than 1.5 torr pressure, etching of the films have been shown. Above the 1.5 torr pressure, however, SiO2 films were nitrided as SiIxNy. Plasma thermal nitridation of SiO2 by addition of small amount (6%) of CF4 to the NH3 showed higher pile-up N concentration in the surface region of SiOxNy film. The higher the nitridation temperature is and the longer the nitridation time is the larger the dielectric constant is. The plasma thermal nitridation of silicon dioxide on silicon causes the flat-band voltage shift based on the formation of the positive charge. The conduction mechanism for SiOxNy films could be elucidated by Fowler-Nordheim tnneling model. By SIMS analysis, surface of the film nitrided in plasma process has less contamination than that of the film nitrided in open-tube process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.54-57
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• 2002

In this study, a new programming method, to minimize the generation of Si-SiO$_2$ interface traps of scaled SONOS flash memory as a function of number of program/erase cycles has been proposed. In the proposed programming method, power supply voltage is applied to the gate, forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim (MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and drain are open. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ prograss/erase cycles can be realized by the proposed programming method. The asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics of scaled SONOS devices because electrical stress applied to the Si-SiO$_2$ interface is reduced by short programming time.

• 한국전기전자재료학회논문지
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• 제16권1호
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• pp.5-10
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• 2003

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.

• 한국재료학회지
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• 제29권8호
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• pp.463-468
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• 2019

The electrical and interfacial properties of $HfO_2/Al_2O_3$ and $Al_2O_3/HfO_2$ dielectrics on AlN/p-Ge interface prepared by thermal atomic layer deposition are investigated by capacitance-voltage(C-V) and current-voltage(I-V) measurements. In the C-V measurements, humps related to mid-gap states are observed when the ac frequency is below 100 kHz, revealing lower mid-gap states for the $HfO_2/Al_2O_3$ sample. Higher frequency dispersion in the inversion region is observed for the $Al_2O_3/HfO_2$ sample, indicating the presence of slow interface states A higher interface trap density calculated from the high-low frequency method is observed for the $Al_2O_3/HfO_2$ sample. The parallel conductance method, applied to the accumulation region, shows border traps at 0.3~0.32 eV for the $Al_2O_3/HfO_2$ sample, which are not observed for the $Al_2O_3/HfO_2$ sample. I-V measurements show a reduction of leakage current of about three orders of magnitude for the $HfO_2/Al_2O_3$ sample. Using the Fowler-Nordheim emission, the barrier height is calculated and found to be about 1.08 eV for the $HfO_2/Al_2O_3$ sample. Based on these results, it is suggested that $HfO_2/Al_2O_3$ is a better dielectric stack than $Al_2O_3/HfO_2$ on AlN/p-Ge interface.