• Journal of KSNVE
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• v.6 no.3
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• pp.305-315
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• 1996

Present paper aims at the correlation of modal characteristics of folding fin between test and analysis using an optimization theory. Folding fin is composed of a movable fin, a base fin, and many functional components related to the folding mechanism. Joint parts of folding fin in FEM are initially modeled as rigid elements resulting some difference between test and analysis in modal characteristics. Therefore, some equivalent springs representing joint parts are introduced to improve the FEM model. The springs were set as design variables, while the frequency difference between test and analysis was set as the object function. Bayesian procedure was ujsed for the minimization.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.74-81
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• 2007

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 1GSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones is proposed. further, a novel layout technique is introduced for compact area. With the clock speed of 1GSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 500MHz, while consuming only 60mW of power. The measured INL and DNL were within $\pm$0.5 LSB, $\pm$0.7 LSB, respectively. The measured SNR was 34.1dB, when the Fin=100MHz at Fs=300MHz. The active chip occupies an area of 0.27$mm^2$ in 0.18um CMOS technology.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.137-147
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• 2013

In this paper, an 1.2V 8b 1GS/s A/D Converter(ADC) based on a folding architecture with a resistive interpolation technique is described. In order to overcome the asymmetrical boundary-condition error of conventional folding ADCs, a novel scheme with an odd number of folding blocks and a fractional folding rate are proposed. Further, a new digital encoding technique with an arithmetic adder is described to implement the proposed fractional folding technique. The proposed ADC employs an iterating offset self-calibration technique and a digital error correction circuit to minimize device mismatch and external noise The chip has been fabricated with a 1.2V 0.13um 1-poly 6-metal CMOS technology. The effective chip area is $2.1mm^2$ (ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$) and the power dissipation is about 350mW including calibration engine at 1.2V power supply. The measured result of SNDR is 46.22dB, when Fin = 10MHz at Fs = 1GHz. Both the INL and DNL are within 1LSB with the self-calibration circuit.

• Journal of the Korea Institute of Military Science and Technology
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• v.22 no.3
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• pp.353-359
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• 2019

In this study, a aerodynamic loads prediction to design a deploying device of folded fin was introduced. In general, resultant flow conditions around the fin are used to obtain deploying moments and required energy. However, when it comes to the air vehicles launched from a mobile platform, more specific flow conditions can be provided. With the conditions, the design criteria can be calculated more realistically. In this study, therefore, aerodynamic moments induced by aerodynamic loads and energy required in deployment were calculated using wind-over-deck(WOD) velocity, combination of a platform velocity and a wind velocity. For the calculation, wind tunnel test was conducted on various angle of attack, side slip angles, and folding angles. It was found that the aerodynamic moments and the energy required in deployment using the non-uniform flow due to the velocity components were less than those using the uniform flow without the components.