• 대한조선학회논문집
• /
• 제45권6호
• /
• pp.611-619
• /
• 2008

In most shipyards Floating Dock-gate System is adapted for dry docks. For the safe launching of ships in dry docks, smooth operation of dock-gate must be guaranteed. So it is very important to grasp its behavior in waves for securing the high productivity and the safety of workers. Its seakeeping ability was estimated numerically at the floating conditions and the free roll decay and the seakeeping model tests of dock-gate was carried out with bilge-keels of 3 different widths which have a scale of 1 to 20. More than 20% decrease of roll motion was observed in irregular beam seas by applying a bilge-keel system to the dock-gate that is long and narrow.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1998년도 추계종합학술대회 논문집
• /
• pp.545-548
• /
• 1998

Thin film SOI(Silicon-On-Insulator) devices exhibit floating body effect. In this paper, SOI NMOSFET is proposed to solve this problem. Some part of gate oxide was considered to be 30nm~80nm thicker than the other normal gate oxide and simulated with TSUPREM-4. The I-V characteristics were simulated with 2D MEDICI mesh. Since part of gate oxide has different oxide thickness in proposed device, the gate electric field strength is not the same throught the gate and consequently the reduction of current kink effect is occurred.

• Journal of information and communication convergence engineering
• /
• 제10권2호
• /
• pp.194-199
• /
• 2012

This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 ${\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
• /
• pp.199-202
• /
• 2004

NFGM(Nano-Floating Gate Memory) is a very prospective candidate memory for the next generation with MRAM, PRAM, PoRAM. Among these memory devices for the next generation, NFGM has a lot of merits such as a simple low cost fabrication process, improved retention time, lower operating voltages, high speed program/erase time and so on. Therefore, many intensive researches for NFGM have been performed to improve device performance and reliability, which depends on the ability to control particle size, size distribution, crystallity, areal particle density and tunneling oxide quality. In this paper, we investigate the researches for NFGM up to recently.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
• /
• pp.1044-1046
• /
• 2009

Here we report the architecture for a non-volatile n-type memory paper field-effect transistor. The device is built using the hybrid integration of natural cellulose fibers (pine and eucalyptus fibers embedded in an ionic resin), which act simultaneously as substrate and gate dielectric, with amorphous GIZO and IZO oxides as gate and channel layers, respectively. This is complemented by the use of continuous patterned metal layers as source/drain electrodes.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
• /
• pp.101-101
• /
• 2007

We fabricated floating gate non-volatile memory devices with Si nanocrystals embedded in $SiN_x$ layer to achieve higher trap density. The average size of Si nanocrystals embedded in $SiN_x$ layer was ranging from 3 nm to 5 nm. The MOS capacitor and MOSFET devices with Si nanocrystals embedded in $SiN_x$ layer were analyzed the charging effects as a function of Si nanocrystals size.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
• /
• pp.107-108
• /
• 2005

Au and $Au/SiO_2$ nanoparticles(NPs) were synthesized by the colloidal method. The formation of Au and $Au/SiO_2$ NPs was confirmed using high resolution transmission electron microscopy (HRTEM). Synthesized solutions were deposited on Si wafer. The electrical properties of structures were measured using a semiconductor analyzer and a LCR meter. Capacitance versus voltage hysterisis curves showed the charge storage effect by Au and $Au/SiO_2$ NPs.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
• /
• pp.130-131
• /
• 2006

차세대 반도체 정보기억장치로서 활발하게 연구되고 있는 나노 부유 게이트 메모리 (Nano Floating Gate Memory) 소자를 위해 필수적인 요소인 나노 크리스탈의 형성을 위하여 다양한 굴절률을 가진 실리콘 질화막 (SiNx)을 형성하고 고온 열처리 (rapid thermal annealing)를 실시하여 나노 크리스탈의 형성과 특성에 대한 연구를 진행하였다. 다양한 굴절률을 가진 실리콘 질화막을 형성한 후 나노 크리스탈의 형성을 위하여 열처리를 수행하였고, photoluminescence (PL)를 통하여 굴절률이 높은 Si-rich SiNx 박막의 고온 열처리를 수행한 실리콘 질화막으로부터 나노 크리스탈의 형성을 확인할 수 있었다. 또한 열처리한 실리콘 질화막 위에 Al을 증착하여 MIS 구조를 형성한 후 Capacitance-Voltage (C-V) 특성을 측정하였으며, $900^{\circ}C$에서 열처리한 박막에서 나노 크리스탈에 의한 메모리 효과를 확인할 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제8권1호
• /
• pp.27-31
• /
• 2008

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2007년도 추계학술대회 논문집
• /
• pp.136-137
• /
• 2007

In this study, a single ZnO nanowire - CdTe nanoparticle nano floating gate memory (NFGM) device is successfully fabricated and characterized their memory effects by comparison of electrical characteristics of ZnO nanowire-based field effect transistor (FET) devices with CdTe nanoparticles embedded in the $Al_2O_3$ gate materials and without the CdTe nanoparticles.