• Title/Summary/Keyword: Flexible Transistor

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Measurements of the Temperature Coefficient of Resistance of CVD-Grown Graphene Coated with PEI (PEI가 코팅된 CVD 그래핀의 저항 온도 계수 측정)

  • Soomook Lim;Ji Won Suk
    • Composites Research
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    • v.36 no.5
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    • pp.342-348
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    • 2023
  • There has been increasing demand for real-time monitoring of body and ambient temperatures using wearable devices. Graphene-based thermistors have been developed for high-performance flexible temperature sensors. In this study, the temperature coefficient of resistance (TCR) of monolayer graphene was controlled by coating polyethylenimine (PEI) on graphene surfaces to enhance its temperature-sensing performances. Monolayer graphene grown by chemical vapor deposition (CVD) was wet-transferred onto a target substrate. To facilitate the interfacial doping by PEI, the hydrophobic graphene surface was altered to be hydrophilic by oxygen plasma treatments while minimizing defect generation. The effect of PEI doping on graphene was confirmed using a back-gated field-effect transistor (FET). The CVD-grown monolayer graphene coated with PEI exhibited an improved TCR of -0.49(±0.03) %/K in a temperature range of 30~50℃.

Study on Design of ZnO-Based Thin-Film Transistors With Optimal Mechanical Stability (ZnO 기반 박막트랜지스터의 기계적 안정성 확보에 관한 연구)

  • Lee, Deok-Kyu;Park, Kyung-Yea;Ahn, Jong-Hyun;Lee, Nae-Eung;Kim, Youn-Jea
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.35 no.1
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    • pp.17-22
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    • 2011
  • ZnO-based thin-film transistors (TFTs) have been fabricated and the mechanical characteristics of electric circuits, such as stress, strain, and deformation are analyzed by the finite element method (FEM). In this study, a mechanical-stability design guide for such systems is proposed; this design takes into account the stress and deformation of the bridge to estimate the stress distribution in an $SiO_2$ film with 0 to 5% stretched on 0.5-${\mu}m$-thick. The predicted buckle amplitude of $SiO_2$ bridges agrees well with experimental results within 0.5% error. The stress and strain at the contact point between bridges and a pad were measured in a previous structural analysis. These structural analysis suggest that the numerical measurement of deformation, SU-8 coating thickness for Neutral Mechanical Plane (NMP) and ITO electrode size on a dielectric layer was useful in enhancing the structural and electrical stabilities.

Plasma Polymerized Styrene for Gate Insulator Application to Pentacene-capacitor (유기박막트랜지스터 응용을 위해 플라즈마 중합된 Styrene 게이트 절연박막)

  • Hwang, M.H.;Son, Y.D.;Woo, I.S.;Basana, B.;Lim, J.S.;Shin, P.K.
    • Journal of the Korean Vacuum Society
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    • v.20 no.5
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    • pp.327-332
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    • 2011
  • Plasma polymerized styrene (ppS) thin films were prepared on ITO coated glass substrates for a MIM (metal-insulator-metal) structure with thermally evaporated Au thin film as metal contact. Also the ppS thin films were applied as organic insulator to a MIS (metal-insulatorsemiconductor) device with thermally evaporated pentacene thin film as organic semiconductor layer. After the I-V and C-V measurements with MIM and MIS structures, the ppS revealed relatively higher dielectric constant of k=3.7 than those of the conventional poly styrene and very low leakage current density of $1{\times}10^{-8}Acm^{-2}$ at electric field strength of $1MVcm^{-1}$. The MIS structure with the ppS dielectric layer showed negligible hysteresis in C-V characteristics. It would be therefore expected that the proposed ppS could be applied as a promising dielectric/insulator to organic thin film transistors, organic memory devices, and flexible organic electronic devices.

The Fabrication of OTFT-OLED Array Using Ag-paste for Source and Drain Electrode (Ag 페이스트를 소스와 드레인 전극으로 사용한 OTFT-OLED 어레이 제작)

  • Ryu, Gi-Seong;Kim, Young-Bae;Song, Chung-Kun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.5
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    • pp.12-18
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    • 2008
  • Ag paste was employed for source and drain electrode of OTFTs and for the data metal lines of OTFT-OLED array on PC(polycarbonate) substrate. We tested two kinds of Ag-pastes such as pastes for 325 mesh and 500 mesh screen mask to examine the pattern ability and electrical performance for OTFTs. The minimum feature size was 60 ${\mu}m$ for 325 mesh screen mask and 40 ${\mu}m$ for 500 mesh screen mask. The conductivity was 60 $m{\Omega}/\square$ for 325 mesh and 133.1 $m{\Omega}/\square$ for 500 mesh. For the OTFT performance the mobility was 0.35 $cm^2/V{\cdot}sec$ and 0.12 $cm^2/V{\cdot}sec$, threshold voltage was -4.7 V and 0.9 V, respectively, and on/off current ratio was ${\sim}10^5$, for both screen masks. We applied the 500 mash Ag paste to OTFT-OLED array because of its good patterning property. The pixel was composed of two OTFTs and one capacitor and one OLED in the area of $2mm{\times}2mm$. The panel successfully worked in active mode operation even though there were a few bad pixels.

The improvement of electrical properties of InGaZnO (IGZO)4(IGZO) TFT by treating post-annealing process in different temperatures.

  • Kim, Soon-Jae;Lee, Hoo-Jeong;Yoo, Hee-Jun;Park, Gum-Hee;Kim, Tae-Wook;Roh, Yong-Han
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.08a
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    • pp.169-169
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    • 2010
  • As display industry requires various applications for future display technology, which can guarantees high level of flexibility and transparency on display panel, oxide semiconductor materials are regarded as one of the best candidates. $InGaZnO_4$(IGZO) has gathered much attention as a post-transition metal oxide used in active layer in thin-film transistor. Due to its high mobility fabricated at low temperature fabrication process, which is proper for application to display backplanes and use in flexible and/or transparent electronics. Electrical performance of amorphous oxide semiconductors depends on the resistance of the interface between source/drain metal contact and active layer. It is also affected by sheet resistance on IGZO thin film. Controlling contact/sheet resistance has been a hot issue for improving electrical properties of AOS(Amorphous oxide semiconductor). To overcome this problem, post-annealing has been introduced. In other words, through post-annealing process, saturation mobility, on/off ratio, drain current of the device all increase. In this research, we studied on the relation between device's resistance and post-annealing temperature. So far as many post-annealing effects have been reported, this research especially analyzed the change of electrical properties by increasing post-annealing temperature. We fabricated 6 main samples. After a-IGZO deposition, Samples were post-annealed in 5 different temperatures; as-deposited, $100^{\circ}C$, $200^{\circ}C$, $300^{\circ}C$, $400^{\circ}C$ and $500^{\circ}C$. Metal deposition was done on these samples by using Mo through E-beam evaporation. For analysis, three analysis methods were used; IV-characteristics by probe station, surface roughness by AFM, metal oxidation by FE-SEM. Experimental results say that contact resistance increased because of the metal oxidation on metal contact and rough surface of a-IGZO layer. we can suggest some of the possible solutions to overcome resistance effect for the improvement of TFT electrical performances.

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