• 정보처리학회논문지D
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• 제14D권7호
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• pp.719-726
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• 2007

최근 NAND 플래시 메모리는 충격에 강한 내구력과, 저 전력 소비, 그리고 비휘발성이라는 특징 때문에 MP3 플레이어, 모바일 폰, 노트북과 같은 다양한 이동 컴퓨팅 장비의 저장 장치로 사용되고 있다. 그러나 플래시 메모리의 특수한 하드웨어적 특징 때문에 디스크 기반의 시스템을 플래시 메모리상에 곧바로 적용 하는 것은 여러 단점들을 발생 시킬 수 있다. 특히 B트리가 구축될 때 레코드의 삽입, 삭제연산 및 노드 분할 연산은 많은 중첩쓰기 연산을 발생하기 때문에 플래시 메모리의 성능을 심각하게 저하시킬 것이다. 본 논문에서는 IBSF로 불리는 효율적인 버퍼 관리 기법을 제안한다. 이것은 색인 단위에서 중복된 색인 단위를 제거하여 버퍼가 채워지는 시간을 지연시키기 때문에 B트리를 구축할 때 플래시 메모리에 데이터를 쓰는 횟수를 줄인다. 또한 다양한 실험을 통하여 IBSF 기법이 기존에 제안되었던 BFTL 기법보다 좋은 성능을 보이는 것을 증명한다.

• 반도체디스플레이기술학회지
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• 제9권2호
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• pp.67-72
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• 2010

Recently increasing application of flash memory in mobile and ubiquitous related devices is due to its non-volatility, fast response time, shock resistance and low power consumption. Following this trend, SSD(Solid State Disk) using multiple flash chips, instead of hard-drive based storage system, started to widely used for its advantageous features. However, flash memory based storage subsystem should resolve the performance bottleneck for writing in perspective of speed and lifetime according to its disadvantageous physical property. In order to provide tangible performance, solutions are studied in aspect of reclaiming of invalid regions by decreasing the number of erasures and distributing the erasures uniformly over the whole memory space as much as possible. In this paper, we study flash memory recycling algorithms with multiple management units and demonstrate that the proposed algorithm provides feasible performance. The proposed method utilizes the partitions of the memory space by utilizing threshold values and reconfigures the management units if necessary. The performance of the proposed policies is evaluated through a number of simulation based experiments.

• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.112-117
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• 2020

NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.

• 한국컴퓨터정보학회논문지
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• 제25권2호
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• pp.21-29
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• 2020

IT 산업 환경에서 모바일 데이터의 수요 증가로 인해 NAND 플래시 메모리의 사용이 지속적으로 증가하고 있다. 하지만, 플래시 메모리의 소거 동작은 긴 대기 시간과 높은 소비 전력을 요구하여 각 셀의 수명을 제한한다. 따라서 쓰기와 삭제 작업을 자주 수행하면 플래시 메모리의 성능과 수명이 단축된다. 이런 문제를 해결하기 위해 디스크 버퍼를 이용, 플래시 메모리에 할당되는 쓰기 및 지우기 연산을 감소시켜 플래시 메모리의 성능을 향상시키는 기술이 연구되고 있다. 본 논문에서는 쓰기 횟수를 최소화하기 위한 CPWL 기법을 제안한다. CPWL 기법은 버퍼 메모리 액세스 패턴에 따라 읽기 및 쓰기 페이지를 나누어 관리한다. 이렇게 나뉜 페이지를 정렬하여 쓰기 횟수를 줄이고 결과적으로 플래시 메모리의 수명을 늘리고 에너지 소비를 감소시킨다.

• Journal of Information Processing Systems
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• 제2권3호
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• pp.147-152
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• 2006

NAND flash memory-based embedded systems are becoming increasingly common. These embedded systems have to provide a fast boot time. In this paper, we have designed and proposed a flash file system for embedded systems that require fast booting. By using a Flash Image Area, which keeps the latest flash memory information such as types and status of all blocks, the file system mounting time can be reduced significantly. We have shown by experiments that our file system outperforms YAFFS and RFFS.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 컴퓨터소사이어티 추계학술대회논문집
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• pp.15-18
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• 2003

Flash memory becomes more important for its fast access speed, low-power, shock resistance and nonvolatile storage. But its native restrictions that have limited 1ifetime, inability of update in place, different size unit of read/write and erase operations need to managed by FTL(Flash Translation Layer). FTL has to control the wear-leveling, address mapping, bad block management of flash memory. In this paper, we focuses on the fast access to address mapping table and proposed the way of faster valid page search in the flash memory using the VPLT(Valid Page Lookup Table). This method is expected to decrease the frequency of access of flash memory that have an significant effect on performance of read and block-transfer operations. For the validations, we implemented the FTL based on Windows CE platform and obtained an improved result.

• 대한전자공학회논문지SD
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• 제45권3호
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• pp.94-100
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• 2008

컴팩트 플래시 메모리와 같은 휴대용 저장장치 표준에서는 플래시 메모리 시스템 소프트웨어인 FTL(Flash Translation Layer)이 필요하다. 본 논문에서는 논리 주소를 물리 주소로 빠르게 변환하기 위해 Clustered Hash Table과 2단계 소프트웨어 캐시 기법을 사용하여 FTL을 설계하였다. 실험 결과 본 논문에서 제안한 CFTL이 잘 알려진 NFTL과 AFTL보다 각각 13%, 8% 이상 주소 변환 성능이 빠르고 AFTL보다 메모리 사용량을 75% 이상 감소시켰다.

• Journal of Information Technology Applications and Management
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• 제13권2호
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• pp.115-126
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• 2006

Recently, flash memories are one of best media to support portable computer's storages in mobile computing environment. We propose a new transaction recovery scheme for a flash memory database environment which is based on a flash media file system. We improved traditional shadow paging schemes by reusing old data pages which are supposed to be invalidated in the course of writing a new data page in the flash file system environment. In order to reuse these data pages, we exploit deferred cleaning list structure in our flash memory shadow paging (FMSP) scheme. FMSP scheme removes the additional storage overhead for keeping shadow pages and minimizes the I/O performance degradation caused by data page distribution phenomena of traditional shadow paging schemes. We also propose a simulation model to show the performance of FMSP. Based on the results of the performance evaluation, we conclude that FMSP outperforms the traditional scheme.

• ETRI Journal
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• 제30권6호
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• pp.790-798
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• 2008

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.932-935
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• 2002

In this paper, we introduce new FTL(Flash Translation Layer) driver algorithm that tolerate the power off errors. FTL driver is the software that provide the block device interface to the upper layer software such as file systems or application programs that using the flash memory as a block device interfaced storage. Usually, the flash memory is used as the storage devices of the mobile system due to its low power consumption and small form factor. In mobile system, the state of the power supplement is not stable, because it using the small sized battery that has limited capacity. So, a sudden power off failure can be occurred when we read or write the data on the flash memory. During the write operation, power off failure may introduce the incomplete write operation. Incomplete write operation denotes the inconsistency of the data in flash memory. To provide the stable storage facility with flash memory in mobile system, FTL should provide the fault tolerance against the power off failure. SSR (Simple Sector Remapper) is a fault tolerant FTL driver that provides block device interface and also provides tolerance against power off errors.