• Proceedings of the Korea Information Processing Society Conference
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• 2012.04a
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• pp.1121-1124
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• 2012

열-지향 데이터베이스 시스템인 C-Store는 많은 상용 데이터베이스 시스템과는 달리 데이터를 행(row) 위주가 아닌 열(column) 위주로 저장을 하여, 데이터 웨어하우스와 같이 주로 읽기 IO를 유발하는 환경에서 데이터의 전송량을 줄임으로써, 높은 성능을 보였다. 본 논문에서는 대표적인 열 지향 저장 DBMS인 C-Store와 행 위주의 저장구조를 사용하는 기존 DBMS와의 차이점을 알아보고, C-Store의 저장장치로 하드디스크와 차세대 저장장치로 주목받고 있는 플래시 SSD(Solid State Disk)를 사용하였을 때, 발생할 수 있는 장단점에 대해 분석하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.143-150
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• 2013

Solid-state disks (SSDs) have been widely used by high-performance personal computers or servers due to its good characteristics and performance. The NAND flash-based SSDs, which take large portion of the whole NAND flash market, are the major type of SSDs. They usually integrate a cache buffer which is built from DRAM and uses the write-back policy for better performance. Unfortunately, the policy makes existing scheduling methods less effective at the I/F level of SSDs Therefore, in this paper, we propose a scheduling method for the I/F with consideration of the cache buffer. The proposed method considers the hit/miss status of cache buffer and gives higher priority to the read requests. As a result, the requests whose data is hit on the cache buffer can be handled in advance and the read requests which have larger effects on the whole system performance than write requests experience shorter latency. The experimental results show that the proposed scheduling method improves read latency by 26%.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.251-258
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• 2012

Recently, NAND Flash memory structure is evolving from SDR (Single Data Rate) to high speed DDR(Double Data Rate) to fulfill the high performance requirement of SSD and SSS. Accordingly, the proper ways of transferring data that latches valid data stably and minimizing data skew between pins by using PHY(Physical layer) circuit techniques have became new issues. Also, rapid growth of speed in NAND flash increases the operating frequency and power consumption of NAND flash controller. Internal voltage variation margin of NAND flash controller will be narrowed through the smaller geometry and lower internal operating voltage below 1.5V. Therefore, the increase of power budge deviation limits the normal operation range of internal circuit. Affection of OCV(On Chip Variation) deteriorates the voltage variation problem and thus causes internal logic errors. In this case, it is too hard to debug, because it is not functional faults. In this paper, we propose new architecture that maintains the valid timing window in cost effective way under sudden power fluctuation cases. Simulation results show that the proposed technique minimizes the data skew by 379% with reduced area by 20% compared to using PHY circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.291-302
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• 2013

NAND flash memory (NFM) based storage devices, e.g. Solid State Drive (SSD), are rapidly replacing conventional storage devices, e.g. Hard Disk Drive (HDD). As NAND flash memory technology advances, its specification has evolved to support denser cells and larger pages and blocks. However, efforts to fully understand their impacts on design objectives such as performance, power, and cost for various applications are often neglected. Our research shows this recent trend can adversely affect the design objectives depending on the characteristics of applications. Past works mostly focused on improving the specific design objectives of NFM based systems via various architectural solutions when the specification of NFM is given. Several other works attempted to model and characterize NFM but did not access the system-level impacts of individual parameters. To the best of our knowledge, this paper is the first work that considers the specification of NFM as the design parameters of NAND flash storage devices (NFSDs) and analyzes the characteristics of various synthesized and real traces and their interaction with design parameters. Our research shows that optimizing design parameters depends heavily on the characteristics of applications. The main contribution of this research is to understand the effects of low-level specifications of NFM, e.g. cell type, page size, and block size, on system-level metrics such as performance, cost, and power consumption in various applications with different characteristics, e.g. request length, update ratios, read-and-modify ratios. Experimental results show that the optimized page and block size can achieve up to 15 times better performance than the conventional NFM configuration in various applications. The results can be used to optimize the system-level objectives of a system with specific applications, e.g. embedded systems with NFM chips, or predict the future direction of NFM.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.539-545
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• 2015

Deduplication technique can expand the lifespan and capacity of flash memory-based storage devices by eliminating duplicated write operations. The deduplication techniques can be classified into two approaches, i.e., online and offline approaches. We propose an offline deduplication technique that uses a lightweight hash algorithm, whereas the previous offline technique uses a high-cost hash algorithm. Therefore, the memory space for caching hash values can be reduced, and more pages can be examined for deduplication during short idle intervals. As a result, it can provide shorter write latencies compared to the online approach, and can show low garbage collection costs compared to the previous offline deduplication technique.

• Proceedings of the Korean Society of Computer Information Conference
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• 2018.07a
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• pp.357-359
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• 2018

최근 메모리 반도체 시장은 SD(Secure Digital) 메모리 카드, SSD(Solid State Drive)등의 보급률 증가로 메모리 반도체의 시장이 대규모로 증가하고 있다. 메모리 반도체는 개인용 컴퓨터 뿐만 아니라 스마프폰, 테플릿 PC, 교육용 임베디드 보드 등 다양한 산업에서 이용 되고 있다. 또한 메모리 반도체 생산 업체가 대규모로 메모리 반도체 산업에 투자하면서 메모리 반도체 시장은 대규모로 성장되었다. 플래시 메모리는 크게 NAND-Type과 NOR-Type으로 나뉘며 플로팅 게이트 셀의 전압의 따라 SLC(Single Level Cell)과 MLC(Multi Level Cell) 그리고 TLC(Triple Level Cell)로 구분 된다. SLC 및 MLC NAND-Type 플래시 메모리는 많은 연구가 진행되고 이용되고 있지만, TLC NAND-Tpye 플래시 메모리는 많은 연구가 진행되고 있지 않다. 본 논문에서는 기존에 제안된 SLC 및 MLC NAND-Type 플래시 메모리에서 제안된 큐브 패턴을 TLC NAND-Type 플래시 메모리에서 적용 가능한 큐브 패턴 및 알고리즘을 제안한다.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.377-380
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• 2007

플래시 메모리는 무게, 내구성, 전력 소비량 측면에서 기존 디스크보다 우수하기 때문에 주로 휴대용 기기의 저장장치로 사용되었다. 최근에는 집적도가 향상되면서 SSD(Solid State Disk)형태로 노트북에서도 활용되고 있다. 이러한 플래시 메모리는 제자리 갱신이 불가능한 특징 때문에 저장장치로 사용하기 위해서는 FTL(Flash Memory Translation Layer)이라는 주소사상 소프트웨어가 필요하다. 그리고 FTL은 블록을 재활용하기 위해 병합 연산을 수행하게 되는데 이 병합 연산의 비용이 시스템 성능에 큰 영향을 미친다. 아울러 FTL 상에서 동작하는 파일 시스템의 경우도 디스크 기반 파일 시스템과 같이 단편화 문제로 인한 성능 저하가 발생하게 된다. 본 논문에서는 플래시 메모리 기반 파일 시스템에서 단편화 현상을 줄이기 위해 FTL의 병합동작의 특성을 활용한 조각 모음 기법을 제안한다. 실험결과는 제안한 기법이 결국 FTL에서 병합 연산의 비용을 줄임으로써 성능을 향상시킬 수 있음을 보여준다.

• Journal of KIISE
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• v.42 no.2
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• pp.169-176
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• 2015

The atomic write technique is a good solution to solve the problem of the double write buffer. The atomic write technique needs modified I/O subsystems (i.e., file system and I/O schedulers) and a special SSD that guarantees the atomicity of the write request. In this paper, we propose the writing unit aligned block allocation technique (for EXT4 file system) and the merge prevention of requests technique for the CFQ scheduler. We also propose an atomic write-supporting SSD which stores the atomicity information in the spare area of the flash memory page. We evaluate the performance of the proposed atomic write scheme in MariaDB using the tpcc-mysql and SysBench benchmarks. The experimental results show that the proposed atomic write technique shows a performance improvement of 1.4~1.5 times compared to the double write buffer technique.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.11
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• pp.409-418
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• 2014

The amount of data located in storage servers has dramatically increased with the growth in cloud and social networking services. Storage systems with very large capacities may suffer from poor reliability and long latency, problems which can be addressed by the use of a hybrid disk, in which mechanical and flash memory storage are combined. The Linux-based SSD(solid-state disk) uses a caching technique based on the DM-cache utility. We assess the limitations of DM-cache by evaluating its performance in diverse environments, and identify problems with the caching policy that it operates in response to various commands. This policy is effective in reducing latency when Linux is running in native mode; but when Linux is installed as a guest operating systems on a virtual machine, the overhead incurred by caching actually reduces performance.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.7
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• pp.508-519
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• 2007

Flash memory based storage has been used in various mobile systems and now is to be used in Laptop computers in the name of Solid State Disk. The Flash memory has not only merits in terms of weight, shock resistance, and power consumption but also limitations like erase-before-write property. To overcome these limitations, Flash memory based storage requires special address mapping software called FTL(Flash-memory Translation Layer), which often performs merge operation for block recycling. In order to reduce block recycling cost in NAND Flash memory based storage, we introduce another block recycling scheme which we call migration. As a result, the FTL can select either merge or migration depending on their costs for each block recycling. Experimental results with Postmark benchmark and embedded system workload show that this cost-based selection of migration/merge operation improves the performance of Flash memory based storage. Also, we present a solution of macroscopic optimal migration/merge sequence that minimizes a block recycling cost for each migration/merge combination period. Experimental results show that the performance of Flash memory based storage can be more improved by the macroscopic optimization than the simple cost-based selection.