• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.286-291
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• 2015

For highly scalable NAND flash memory applications, a compact ($4F^2/cell$) nonvolatile memory architecture is proposed and investigated via three-dimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

• 한국IT서비스학회지
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• 제5권3호
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• pp.165-172
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• 2006

In this paper, we designed a new type of X-internet framework by using Flash component and server service API and analyzed its performance. Proposed X-internet framework uses Flash MX Professional 2004, Java, and software which opened middleware and database. Since proposed framework use the server service API that we developed in this paper and Flash player, this framework does not need server module. Proposed framework enables to obtain design with dynamic user interface compare to Web application and enables to reduce development time. In analytical results, it has been shown that proposed x-internet framework have efficient characteristics such as network traffic, low development cost and dynamic user interface implementation. Since proposed X-internet framework can operate in environment of current developer friendly, it is useful for development of various new application programs and we confirm it through Flash web mail implementation by using proposed x-internet framework.

• 한국연소학회지
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• 제20권2호
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• pp.1-13
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• 2015

Drying, which is the oldest and most energy-intensive process, is an essential process for treatment of solid product. The specific procedure to design and evaluate the dryers, which are a rotary kiln dryer and a flash dryer, in case of drying the high-moisture coal was described. From determination of size to the heat and mass balance in one-dimensional model were conducted to evaluate the performance of dryers. Heat consumption, inlet gas temperature and size of the dryers were compared between a rotary kiln dryer and a flash dryer. Further considerations to evaluate the reactor elaborately were also discussed. Performance simulation of dryers along with the design procedure described here will provide helpful basis for understanding the concept of reactor design.

• KIEE International Transactions on Electrophysics and Applications
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• 제5C권1호
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• pp.14-17
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• 2005

In this paper, an automated methodology for generating model parameters considering real manufacturing processes is presented with verified results. In addition, the outcomes of applications to the next generation of flash memory devices using the parameters calibrated from the process specification decision are analyzed. The test vehicle is replaced with a well-calibrated TCAD simulation. First, the calibration methodology is introduced and tested for a flash memory device. The calibration errors are less than 5% of a full chip operation, which is acceptable to designers. The results of the calibration are then used to predict the I-V curves and the model parameters of various transistors for the design of flash devices.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2001년도 추계종합학술대회
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• pp.567-570
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• 2001

In this paper, we proposed flash memory design method for image and voice recoder based on the standard imageㆍvoice codec algorithm. For implementation of this method we designed image voice browser which is application system of flash memory and card using GDS30C6001 USB controller. To process image and voice data we designed root directory of image and voice files repectively. To extend application of image and voice data we added various information to the system.

• 한국정보전자통신기술학회논문지
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• 제12권3호
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• pp.312-320
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• 2019

본 논문에서는 110nm eFlash 셀을 사용한 512Kb eFlash IP를 설계하였다. eFlash 셀의 프로그램, 지우기와 읽기 동작을 만족시키는 row 구동회로(CG/SL 구동회로), write BL 구동회로( write BL 스위치 회로와 PBL 스위치 선택 회로), read BL 스위치 회로와 read BL S/A 회로와 같은 eFlash 코어회로(Core circuit)를 제안하였다. 그리고 프로그램 모드에서 9.5V와 erase 모드에서 11.5V의 VPP(Boosted Voltage) 전압을 공급하는 VPP 전압 발생기회로는 기존의 단위 전하펌프 회로로 cross-coupled NMOS 트랜지스터를 사용하는 대신 body 전압을 ground에 연결된 12V NMOS 소자인 NMOS 프리차징 트랜지스터의 게이트 노드 전압을 부스팅하는 회로를 새롭게 제안하여 VPP 단위 전하펌프의 프리차징 노드를 정상적으로 VIN(Input Voltage) 전압으로 프리차징 시켜서 VPP 전하펌프 회로의 펌핑 전류를 증가시켰다. 펌핑 커패시터로는 PMOS 펌핑 커패시터에 비해 펌핑전류가 크고 레이아웃 면적이 작은 12V native NMOS 펌핑 커패시터를 사용하였다. 한편 110nm eFlash 공정을 기반으로 설계된 512Kb eFlash 메모리 IP의 레이아웃 면적은 $933.22{\mu}m{\times}925{\mu}m(=0.8632mm^2)$이다.

• 한국산학기술학회논문지
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• 제4권3호
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• pp.177-182
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• 2003

Flash memory는 device 특성상 peripheral circuit을 구성하는 transistor의 종류가 다양하고, 이에 따른 각 transistor의 동작 전압 영역이 넓다. 이에 따라 설계 초기의 전기적 특성 사양 결정을 위해서는, 실리콘상에서 소자의 scale down에 따른 전기적 특성을 선 검증하는 과정이 필수적이었으며, 이로 인해 설계 및 소자 개발의 기간을 단축하기 어려웠다. 본 연구에서는 TCAD tool을 사용하여 실리콘상에서의 제작 공정을 거치지 않고, 효과적으로 model parameter를 생성할 수 있도록 하는 방법을 제안하여 전기적 특성 사양 결정과 설계 단계의 시간 지연을 감소할 수 있도록 한다. 또한 성공적 TCAD tool적용을 위해 필요한 process/device simulator의 calibration methodology와 이를 flash 메모리 소자에 대해 적용 검증한 결과를 분석한다.

• 대한임베디드공학회논문지
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• 제13권5호
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• pp.253-259
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• 2018

Recently, small satellite industries are rapidly changing. Demand for high performance small satellites is increasing with the expansion of Earth Observation Satellite market. A next-generation small satellites require a higher resolution image storage capacity than before. However, there is a problem that the HW configuration of the existing small satellite image storage device could not meet these requirements. The conventional data storing system uses SDRAM to store image data taken from satellites. When SDRAM is used in small satellite platform of a next generation, there is a problem that the cost of physical space is eight times higher and satellite price is two times higher than NAND Flash. Using the same satellite hardware configuration for next-generation satellites will increase the satellite volume to meet hardware requirements. Additional cost is required for structural design, environmental testing, and satellite launch due to increasing volume. Therefore, in order to construct a low-cost, high-efficiency system. This paper shows a next-generation solid state recorder unit (SSRU) using MRAM and NAND Flash instead of SDRAM. As a result of this research, next generation small satellite retain a storage size and weight and improves the data storage space by 15 times and the storage speed by 4.5 times compare to conventional design. Also reduced energy consumption by 96% compared to SDRAM based storage devices.

• Journal of Information Processing Systems
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• 제2권3호
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• pp.147-152
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• 2006

NAND flash memory-based embedded systems are becoming increasingly common. These embedded systems have to provide a fast boot time. In this paper, we have designed and proposed a flash file system for embedded systems that require fast booting. By using a Flash Image Area, which keeps the latest flash memory information such as types and status of all blocks, the file system mounting time can be reduced significantly. We have shown by experiments that our file system outperforms YAFFS and RFFS.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.647-648
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• 2008

Traditional FTL and flash file systems based of NAND flash memory may not be adaptively applied to new fusion flash memory which combines the advantages of NAND and NOR flash memory. In this paper, we propose a FTL performance measurement tool using Multi Block Erase function of fusion flash memory. The performance measurement tool shows that multi block erase function can be effectively utilized in performance enhancement of garbage collection for fusion flash memory.