• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.4
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• pp.613-618
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• 2015

This paper proposed a low power CMOS Flash-SAR A/D converter which consists of a Flash A/D converter for 2 most significant bits and a SAR A/D converter with capacitor D/A converter for 8 least significant bits. Employment of a Flash A/D converter allows the proposed circuit to enhance the conversion speed. The SAR A/D converter with capacitor D/A converter provides a low power dissipation. The proposed A/D converter consumes $136{\mu}W$ with a power supply of 1V under a $0.18{\mu}m$ CMOS process and achieves 9.16 effective number of bits for sampling frequency up to 2MHz. Therefore it results in 120fJ/step of Figure of Merit (FoM).

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.54-61
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• 2008

This paper presents a new TIQ based CMOS flash 6-bit ADC to process digital signal in real time. In order to improve the conversion speed of ADC by designing new logic or layout of ADC circuits, a new design method is proposed in encoding logic circuits. The proposed encoding circuits convert analog input into digitally encoded double base number system(DBNS), which uses two bases unlike the normal binary representation scheme. The DBNS adopts binary and ternary radix to enhance digital arithmetic processing capability. In the DBNS, the addition and multiplication can be processed with just shift operations only. Finding near canonical representation is the most important work in general DBNS. But the main disadvantage of DBNS representation in ADC is the fan-in problem. Thus, an equal distribution algorithm is developed to solve the fan-in problem after assignment the prime numbers first. The conversion speed of simulation result was 1.6 GSPS, at 1.8V power with the Magna $0.18{\mu}m$ CMOS process, and the maximum power consumption was 38.71mW.

• Smart Media Journal
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• v.2 no.1
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• pp.8-16
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• 2013

The significant enhancement of the edge portion of computer networks including user-side machines and last mile network links encourages the research of the overlay network based data dissemination systems. Varieties of overlay network based data dissemination systems has distinct purposes, and each of them has a proper structure of an overlay network and a efficient communication protocol. In this paper, overlay network based data dissemination systems for Flash Dissemination, whose target is the distribution of relatively small size data to very large number of recipients within very short time, are explored. Mainly two systems, RECREW and FaReCAST, are introduced and analyzed in the aspects of design considerations for overlay networks and communication protocols. According to evaluations for flash dissemination scenarios, it is observed that the proposed overlay network based flash dissemination systems outperforms the previous overlay network based multicasting systems, in terms of the reliability and the dissemination delay. Moreover, the theoretical analysis of the reliability of data dissemination is provided by analysing FaReCAST.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.33 no.2
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• pp.42-51
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• 2015

• 한국HCI학회:학술대회논문집
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• 2009.02a
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• pp.1020-1023
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• 2009

It had been longer that the design mock-up was made mainly in order to test products. These days, it seems to be main stream that the working mockup is done because designers consider not only the design but also usability. In this study, the modular hardware toolkit, complimentary with Adobe Flash, was developed so that it solves the problem, the electronic hardware which the designers should struggle to make by themselves. This result thing could help the time of the design process to be short and contribute to make robust system rapidly.

• Transactions of Materials Processing
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• v.17 no.8
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• pp.600-606
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• 2008

In closed-die hot forging, a billet is formed in dies such that the flow of metal from the die cavity is restricted. Some parts can be forged in a single set of dies, whilst others, due to shape complexity and material flow limitations, must be shaped in multi sets of dies. The purpose of a performing operation is to distribute the volume of the parts such that material flow in the finisher dies will be sound. This study focused on the design of preforms, flash thickness and land width by theoretical calculation and finite element analysis, to manufacture the super hot forging product, 70MC type piston crown used in marine engine. The optimal design of preforms by the finite element analysis and the design experiment achieves adequate metal distribution without any defects and guarantees the minimum forming load and fully filling of the cavity of the die for producing the large piston crown. The maximum loads obtained by finite element analysis are compared with the results of experiments. The loads of the analysis have good agreements with those of the experiment. Results obtained using DEFORM-2D enable the designer and manufacturer of super hot forging dies to be more efficient in this field.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.231-232
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• 2017

This paper describes the design and implementation of a 2.5kW (500V, 5A) simmer circuit that maintains the ionization of xenon gas inside the lamp. The design is based on a LCC resonant converter in continuous conduction mode (CCM) with above resonant frequency to take advantage of high power density from using parasitic elements such as the leakage inductance in a power transformer. In addition, since the converter has current source output characteristics, it is suitable for maintaining ionization of the lamp having the negative resistance load characteristic. To verify this converter design, PSpice modeling was performed. Finally, the developed simmer circuit is verified by a resistive load of rated performance and the Ionization maintenance operation of the xenon flash lamp.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.1-8
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• 2005

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation, we present an Interpolation type architecture. In order to overcome the problems of high speed operation, a novel One-zero Detecting Encoder, a circuit to reduce the Reference Fluctuation, an Averaging Resistor and a Track & Hold, a novel Buffered Reference for the improved SNR are proposed. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply and occupies chip area of 977um $\times$ 1040um. Experimental result show that SNDR is 36.25 dB when sampling frequency is 2GHz and INL/DNL is $\pm$0.5LSB at static performance.

• Archives of design research
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• v.14 no.4
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• pp.217-226
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• 2001

In 21st century, with the rapid development of Information technologies, a new form of postgraduate courses on multimedia has emerged. The curriculum of that course is consisted of a combination of design related fields and computer science. In this thesis, I analyzed problems of design education come from multimedia departments of 2-year colleges. This form of departments result in the reduction of design related courses and that is also reduction of basic design rather than multimedia. But, for the desirable multimedia design education, the functional aspects of multimedia must be harmonized with the artistic aspects. For these reason, I developed a course of study on multimedia design. It consists of theoretical studies about design principles, actual training on flash application, and individual projects accomplishments. And on the basis of this results, case studies of 3 subjects were done in a semester.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.10
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• pp.1-8
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• 1999

In this paper, we have studies the transport mechanism and origin of SILC for the various thickness of wet oxide. Also, SILC characteristics of $N_2O$ annealed oxide was included in this study. We made the flash memory cell with $N_2O$ annealed oxide of 60Athick under $0.25{\mu}m$ design rule, and measured the characteristics of the cell. As a result, we have found that the origin of SILC is due to the trap formed inside of the oxide layer by electrical stress. And we reached the conclusion that the transport mechanism of SILC is ruled by the modified F-N tunneling if the electric field is lower than 8MV/cm or typical F-N tunneling if the electric field is higher than 8MV/cm. We could also confirm the fact that $N_2O$ annealed oxide of 60Athick have an improved resistance effect against SILC. In case that we apply $N_2O$ annealed oxide of 60Athick to the flash memory, we could confirm $10^6$ times endurance and more than 10 years drain disturb, and could get 8V programmable flash memory characteristics.