• Clean Technology
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• v.26 no.3
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• pp.161-167
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• 2020

For the design of the prevention and mitigation measures in process industries involving flammable substances, reliable safety data are required. An important property used to estimate the risk of fire and explosion for a flammable liquid is the flash point. Flammability is an important factor to consider when developing safe methods for storing and handling solids and liquids. In this study, the flash point data were measured for the binary systems {2-butanol + 2,2,4-trimethylpentane}, {2-butanol + methylcyclohexane} and {2-butanol + toluene} at 101.3 kPa. Experiments were performed according to the standard test method (ASTM D 3278) using a Stanhope-Seta closed cup flash point tester. A minimum flash point behavior was observed in the binary systems as in the many cases for the hydrocarbon and alcohol mixture that were observed. The measured flash points were compared with the predicted values calculated via the following activity coefficient (GE) models: Wilson, Non-Random Two-Liquid (NRTL), and UNIversal QUAsiChemical (UNIQUAC) models. The predicted data were only adequate for the data determined by the closed-cup test method and may not be appropriate for the data obtained from the open-cup test method because of its deviation from the vapor liquid equilibrium. The predicted results of this work can be used to design safe petrochemical processes, such as the identification of safe storage conditions for non-ideal solutions containing flammable components.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.11
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• pp.914-920
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• 2000

When the charge-trap type SONOS(polysilicon-oxide-nitride-oxide-semiconductor) cells are used to flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM(Nonvolatile Semiconductor Memory) cells were fabricated using 0.35 ㎛ standard memory cell embedded logic process including the ONO cell process, based on retrograde twin-well, single-poly, single metal CMOS(Complementary Metal Oxide Semiconductor) process. The thickness of ONO triple-dielectric for the memory cell is tunnel oxide of 24 $\AA$, nitride of 74 $\AA$, blocking oxide of 25 $\AA$, respectively. The program mode(V$\_$g/=7, 8, 9 V, V$\_$s/=V$\_$d/=-3 V, V$\_$b/=floating) and the erase mode(V$\_$g/=-4, -5, -6 V, V$\_$s/=V$\_$d/=floating, V$\_$b/=3 V) by MFN(Modified Fowler-Nordheim) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation(ΔV$\_$th/, S, G$\_$m/) characteristics than channel MFN tunneling operation. Also, the program inhibit conditins of unselected cell for separated source lines NOR-type flash memory application were investigated. we demonstrated that the phenomenon of the program disturb did not occur at source/drain voltage of 1 V∼12 V and gate voltage of -8 V∼4 V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.706-711
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• 2014

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.182-192
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• 2015

In this paper, we introduce how to change the reaction rate as mol concentration when we scan enhanced MRI with GBCA(Gadolinium Based Contrast Agent), Also show the changing patterns depending on diverse MRI sequences which are made by different physical principle. For this study, we made MRI phantom ourselves. We mixed 500 mmol Gadoteridol with Saline in each 28 different containers from 500 to 0 mmol. After that, MR phantom was scanned by physically different MRI sequences which are T1 SE, T2 FLAIR, T1 FLAIR, 3D FLASH, T1 3D SPACE and 3D SPCIR in 1.5T bore. The results were as follows : *T1 Spin echo's Total SI(Signal Intensity) was 15608.7, Max peak was 1352.6 in 1 mmol. *T2 FLAIR's Total SI was 9106.4, Max peak was 0.4 1721.6 in 1 mmol. *T1 FLAIR's Total SI was 20972.5, Max peak was 1604.9 in 1 mmol. *3D FLASH's Total SI was 20924.0, Max peak was 1425.7 in 40 mmol. *3D SPACE 1mm's Total SI was 6399.0, Max peak was 528.3 in 3 mmol. *3D SPACE 5mm's Total SI was 6276.5, Max peak was 514.6 in 2 mmol. *3D SPCIR's Total SI was 1778.8, Max peak was 383.8 in 0.4 mmol. In most sequences, High signal intensity was shown in diluted lower concentration rather than high concentration, And also graph's max peak and pattern had difference value according to the each different sequence. Through this paper which have quantitative result of GBCA's reaction rate depending on sequence, We expect that practical enhanced MR protocol can be performed in clinical field.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.1-8
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• 2005

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation, we present an Interpolation type architecture. In order to overcome the problems of high speed operation, a novel One-zero Detecting Encoder, a circuit to reduce the Reference Fluctuation, an Averaging Resistor and a Track & Hold, a novel Buffered Reference for the improved SNR are proposed. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply and occupies chip area of 977um $\times$ 1040um. Experimental result show that SNDR is 36.25 dB when sampling frequency is 2GHz and INL/DNL is $\pm$0.5LSB at static performance.

• Fire Science and Engineering
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• v.17 no.3
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• pp.1-6
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• 2003

In this study, it reviewed about evacuation performance of a specified Office Building. assessment tools is FAST 3.1.7 (Estimation of Flash Over, Estimation of Layer Height Down Flow Time), SIMULEX 32-bit (Estimation of Evacuation Time), JASMINE 3.25d. (Smoke Flow Assessment of a specified time) Result from Fire Scenario # 1, Flash Over is not generated in Compartment. Evacuation Time is estimated 25.2 sec by SIMULEX 32-bit. layer height until this time (25.2 sec) was estimated 2.4 m by FAST 3.1.7. After ignition until this time (25.2 sec), smoke was not release to the a corridor. In consequence, We concluded that people in building are completing the safe evacuation without the damage of smoke. Result from Fire Scenario # 1, Flash Over generated 6 min 33.2 sec in Compartment. Evacuation Time is estimated 1 min 25.5 sec by SIMULEX 32-bit. layer height down flow time is 1 min 40.8 sec by FAST 3.1.7 and 5 min 23 sec by theoretical calculation. Also, total building evacuation time was estimated 2 min 26.6 sec. After ignition until this time (2 min 26.6 sec), smoke released to the a corridor but it amount was few little. Therefore, generated smoke in compartment not effected to the people in buildings.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.92.2-92.2
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• 2015

Negative-AND (NAND) flash의 대용량 및 소형화로 인해 10 nm급 공정을 도입한 128 Gb NAND flash가 개발된 이래, 공정이 미세화되면서 셀이 작이지고 간격이 좁아지게 되었다. 이로 인해 전자가 누설되는 간섭현상이 심화되게 된다. 이러한 문제를 해결하기 위해 기존 NAND의 평면 구조를 수직으로 적층하는 3D NAND 기술이 개발되었으며 차세대 소자를 위한 필수 기술로 각광받고 있다. 3D NAND에서 channel hole etching시 고 선택 비의 중요도가 증가하여 증착막 보호 역할을 하는 hardmask의 두께가 증가하게 되었으며 기존 하드마스크 대비 내식각성이 2배 이상 향상된 hard material 개발이 필요한 실정이다. 본 연구에서는 dopant에 따른 amorphous carbon layer (ACL)의 etch rate의 변화량을 Raman spectroscopy등의 측정장비를 이용하여 비교분석 하였다. dopant의 각각 유량별에 대한 etch rate 변화의 영향성을 비교하였다. dopant의 유량에 따라 etch rate이 변화하는 것을 관찰할 수 있었으며, 2000 sccm 이후에는 etch rate이 급격히 감소하는 경향을 보였다. Raman 측정결과, etch rate의 감소에 따라 G-peak의 red shift가 발생하였으며 두 peak 간의 차이 값이 etch rate의 변화율과 유사한 경향을 보이는 것을 확인하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.2
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• pp.100-104
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• 2012

Fin-type SONOS (silicon-oxide-nitride-oxide-silicon) flash memory has emerged as novel devices having superior controls over short channel effects(SCE) than the conventional SONOS flash memory devices. However despite these advantages, these also exhibit undesirable characteristics such as corner effect. Usually, the corner effect deteriorates the performance by increasing the leakage current. In this paper, the corner effect of fin-type SONOS flash memory devices is investigate by 3D Process and device simulation and their electrical characteristics are compared to conventional SONOS devices. The corner effect has been observed in fin-type SONOS device. The reason why the memory characteristic in fin-type SONOS flash memory device is not improved, might be due to existing undesirable effect such as corner effect as well as the mutual interference of electric field in the fin-type structure as reported previously.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.6
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• pp.1299-1306
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• 2023

In this paper, we present a system for undesignated cultural heritage management and real-time theft chase, which uses flash-based large-capacity storage. The proposed system is composed of 3 parts, such as a cultural management device, a flash-based server, and a monitoring service for managing cultural heritages and chasing thefts using IoT technologies. However flash-based storage needs methods to overcome the limited lifespan. Therefore, in this paper, we present a system, which uses the disk buffer in flash-based storage to overcome the disadvantage, and evaluate the system performance in various environments. In our experiments, LRU policy shows the number of direct writes in the flash-based storage by 10.7% on average compared with CLOCK and FCFS.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2003.11a
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• pp.97-104
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• 2003

The surface temperature at the interface of bodies in a sliding contact is one of the most important factors influencing the behavior of machine components. So the calculation of the surface temperature at a sliding contact interface has long been an interesting and important subject for tribologist. In this study to verify estimation of temperature rising, calculated temperatures were compared with measured temperatures. It is possible to calculate bulk and flash temperature.