• Proceedings of the Korean Society of Precision Engineering Conference
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• 1994.10a
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• pp.918-923
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• 1994

For the improvement of productivity, the reduction of cost and time for manufacturing is mandatory, especially in the field of electronic industry. The study is concemed with a practical means of systematic assistance to formability estimation and selection of reliable design specification for electronic sheet metal parts. The objective of this research work is to develop a simulation system which helps to analyze the target processes with the finite element method and to acquire available design data quickly and exactly and exactly. The simulation system developed in the study consists of design verification, selection of optimal combination of parameters, knowledge acquisition and graphical user interface(GUI). Design verification is automatically carried out by using the finite element method. A data base management system and nomograms are utilized for knowledge acquistion. The developed system has been applied to some major sheet metal forming operations such as flanging, embossing, bending and blanking. According to the simulated results, the validation of the target processes has been confirmed. Analysis data, estimation rules of formability and graphical representation of the analysis have been employed for the designer's understanfing and evaluation, thus providing a practical means of robot design and evaluation of formability for production electronic sheet metal parts.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.9
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• pp.1786-1792
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• 2015

Random linear network coding (RLNC) is widely employed to enhance the reliability of wireless multicast. In RLNC encoding/decoding, Galois Filed (GF) arithmetic is typically used since all the operations can be performed with symbols of finite bits. Considering the architecture of commercial computers, the complexity of arithmetic operations is constant regardless of the dimension of GF m, if m is smaller than 32 and pre-calculated tables are used for multiplication/division. Based on this, we show that the complexity of RLNC inversely proportional to m. Considering additional overheads, i.e., the increase of header length and memory usage, we determine the practical value of m. We implement RLNC in a commercial computer and evaluate the codec throughput with respect to the type of the tables for multiplication/division and the number of original packets to encode with each other.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.2
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• pp.105-111
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• 2006

Cryptographic application and coding theory require operations in finite field $GF(2^m)$. In such a field, the area and time complexity of implementation estimate by memory and time delay. Therefore, the effort for constructing an efficient multiplier in finite field have been proceeded. Massey-Omura proposed a multiplier that uses normal bases to represent elements $CH(2^m)$ [11] and Agnew at al. suggested a sequential multiplier that is a modification of Massey-Omura's structure for reducing the path delay. Recently, Rayhani-Masoleh and Hasan and S.Kwon at al. suggested a area efficient multipliers for modifying Agnew's structure respectively[2,3]. In [2] Rayhani-Masoleh and Hasan proposed a modified multiplier that has slightly increased a critical path delay from Agnew at al's structure. But, In [3] S.Kwon at al. proposed a modified multiplier that has no loss of a time efficiency from Agnew's structure. In this paper we will propose a multiplier by modifying Rayhani-Masoleh and Hassan's structure and the area-time complexity of the proposed multiplier is exactly same as that of S.Kwon at al's structure for type-II optimal normal basis.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.4B no.4
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• pp.211-216
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• 2004

Inductance characteristics, torque variations and ripple according to current, and position of multi-layer buried magnet synchronous machines with field-weakening operations are presented. The rotor structure optimal design of a buried magnet synchronous machine with high performance is investigated, and optimization results and comparison among design candidates are shown. For the fast and accurate search of multiple optima, the auto-tuning niching genetic algorithm is used and a final solution is selected considering various design factors.

• Journal of Communications and Networks
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• v.12 no.1
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• pp.1-4
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• 2010

As a countermeasure to simple power attack, the unified point addition codes for the elliptic curve cryptosystem were introduced. However, some authors proposed a different kind of power attacks to the codes. This power attack uses the observation that some internal operations in the codes behave differently for addition and doubling. In this paper, we propose a new countermeasure against such an attack. The basic idea of the new countermeasure is that, if one of the input points of the codes is transformed to an equivalent point over the underlying finite field, then the code will behave in the same manner for addition and doubling. The new countermeasure is highly efficient in that it only requires 27(n-1)/3 extra ordinary integer subtractions (in average) for the whole n-bit scalar multiplication. The timing analysis of the proposed countermeasure is also presented to confirm its SPA resistance.

• ETRI Journal
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• v.41 no.6
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• pp.863-872
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• 2019

Elliptic curve cryptography is a relatively lightweight public-key cryptography method for key generation and digital signature verification. Some lightweight curves (eg, Curve25519 and Curve Ed448) have been adopted by upcoming Transport Layer Security 1.3 (TLS 1.3) to replace the standardized NIST curves. However, the efficient implementation of Curve Ed448 on Internet of Things (IoT) devices remains underexplored. This study is focused on the optimization of the Curve Ed448 implementation on low-end IoT processors (ie, 8-bit AVR and 16-bit MSP processors). In particular, the three-level and two-level subtractive Karatsuba algorithms are adopted for multi-precision multiplication on AVR and MSP processors, respectively, and two-level Karatsuba routines are employed for multi-precision squaring. For modular reduction and finite field inversion, fast reduction and Fermat-based inversion operations are used to mitigate side-channel vulnerabilities. The scalar multiplication operation using the Montgomery ladder algorithm requires only 103 and 73 M clock cycles on AVR and MSP processors.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.2
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• pp.49-61
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• 2009

Finite Field multiplication operation is one of the most important operations in the finite field arithmetic. Recently, Fan and Dai introduced a Shifted Polynomial Basis(SPB) and construct a non-pipeline bit-parallel multiplier for $F_{2^n}$. In this paper, we propose a new bit-parallel shifted polynomial basis type I and type II multipliers for $F_{2^n}$ defined by an irreducible trinomial $x^{n}+x^{k}+1$. The proposed type I multiplier has more efficient the space and time complexity than the previous ones. And, proposed type II multiplier have a smaller space complexity than all previously SPB multiplier(include our type I multiplier). However, the time complexity of proposed type II is increased by 1 XOR time-delay in the worst case.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.13-19
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• 2020

In this paper, we propose a multiplexer based scheme that performs modular AB² multiplication using redundant basis over finite field. Then we propose an efficient multiplexer based semi-systolic AB² multiplier using proposed scheme. We derive a method that allows the multiplexers to perform the operations in the cell of the modular AB² multiplier. The cell of the multiplier is implemented using multiplexers to reduce cell latency. As compared to the existing related structures, the proposed AB² multiplier saves about 80.9%, 61.8%, 61.8%, and 9.5% AT complexity of the multipliers of Liu et al., Lee et al., Ting et al., and Kim-Kim, respectively. Therefore, the proposed multiplier is well suited for VLSI implementation and can be easily applied to various applications.

• Journal of Power System Engineering
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• v.13 no.5
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• pp.52-58
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• 2009

A gas turbine consists of an upstream compressor and a downstream turbine with a combustion chamber, and also the compressor and the turbine are generally coupled using a single shaft. Many casing bolts are used to assemble two horizontally separated casings, the gas turbine casing and the compressor casing, in both of axial and vertical directions. Because drilled holes for casing bolts in vertical direction are often too close to drilled holes for casing bolts in axial direction, one can observe cracks in the area frequently during operations of a gas turbine. In this study of the root cause analysis for the cracking initiating from the drilled holes of the casings of a gas turbine, the finite element analysis(FEA) was applied to evaluate the thermal and mechanical characteristics of the casings. By applying the field operation data recorded from combined cycle power plants for FEA, thermal and thermo-mechanical characteristics of a gas turbine are analyzed. The crack is initiated at the geometrical weak point, but it is found that the maximum stress is relieved when the same type of cracks is introduced on purpose during FEA. So, it is verified that the local fracture could be delayed by machining the same type of defects near the hole for casing flange bolts of the gas turbine, where the crack is initiated.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.3
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• pp.113-123
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• 2007

This paper presents a high-performance elliptic curve cryptographic processor over $GF(2^m)$. The proposed design adopts Lopez-Dahab Montgomery algorithm for elliptic curve point multiplication and uses Gaussian normal basis for $GF(2^m)$ field arithmetic operations. We select m=163 which is the smallest value among five recommended $GF(2^m)$ field sizes by NIST and it is Gaussian normal basis of type 4. The proposed elliptic curve cryptographic processor consists of host interface, data memory, instruction memory, and control. We implement the proposed design using Xilinx XCV2000E FPGA device. Based on the FPGA implementation results, we can see that our design is 2.6 times faster and requires significantly less hardware resources compared with the previously proposed best hardware implementation.