• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.9 no.3
• /
• pp.3-12
• /
• 1999

The public key crytptosystem is represented by RSA based on the difficulty of integer factorization and ElGamal cryptosystem based on the intractability of the discrete logarithm problem in a cyclic group G. The index-calculus algorithm for discrete logarithms in GF${$q^n$}^+$ requires an polynomial factorization. The Niederreiter recently developed deterministic facorization algorithm for polynomial over GF$q^n$ In this paper we implemented the arithmetic of finite field with c-language and gibe an implementation of the Niederreiter's algorithm over GF$2^n$ using normal bases.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.7A
• /
• pp.547-556
• /
• 2003

This paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for low-area elliptic curve cryptographic processor. The proposed arithmetic unit, which is linear feed back shift register (LFSR) architecture, is designed by using hardware sharing between the binary GCD algorithm and the most significant bit (MSB)-first multiplication scheme, and it can perform both division and multiplication in GF(2$^{m}$ ). In other word, the proposed architecture produce division results at a rate of one per 2m-1 clock cycles in division mode and multiplication results at a rate of one per m clock cycles in multiplication mode. Analysis shows that the computational delay time of the proposed architecture, for division, is less than previously proposed dividers with reduced transistor counts. In addition, since the proposed arithmetic unit does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and scalability with respect to the field size m. Therefore, the proposed novel architecture can be used for both division and multiplication circuit of elliptic curve cryptographic processor. Specially, it is well suited to low-area applications such as smart cards and hand held devices.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.18 no.3
• /
• pp.33-44
• /
• 2008

The efficiency of pairing based cryptosystems depends on the computation of pairings. pairings is defined over finite fileds GF$(3^m)$ by trinomials due to efficiency. The hardware architectures for pairings have been widely studied. This paper proposes new adder and multiplier for GF(3) which are more efficient than previous results. Furthermore, this paper proposes a new unified adder-subtractor for GF$(3^m)$ based on the proposed adder and multiplier. Finally, this paper proposes new multiplier for GF$(3^m)$. The proposed MSB-first bit-serial multiplier for GF$(p^m)$ reduces the time delay by approximately 30 % and the size of register by half than previous LSB-first multipliers. The proposed multiplier can be applied to all finite fields defined by trinomials.

• Journal of KIISE:Computing Practices and Letters
• /
• v.8 no.1
• /
• pp.88-95
• /
• 2002

In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.9 no.4
• /
• pp.409-416
• /
• 2014

In H/W implementation for the finite field, the use of normal basis has several advantages, especially the optimal normal basis is the most efficient to H/W implementation in $GF(2^m)$. The finite field $GF(2^m)$ with type I optimal normal basis(ONB) has the disadvantage not applicable to some cryptography since m is even. The finite field $GF(2^m)$ with type II ONB, however, such as $GF(2^{233})$ are applicable to ECDSA recommended by NIST. In this paper, we propose a bit-parallel multiplier over $GF(2^m)$ having a type II ONB, which performs multiplication over $GF(2^m)$ in the extension field $GF(2^{2m})$. The time and area complexity of the proposed multiplier is the same as or partially better than the best known type II ONB bit-parallel multiplier.

• Journal of KIISE:Computer Systems and Theory
• /
• v.35 no.7
• /
• pp.327-331
• /
• 2008

Optimal Extension Fields (OEFs) are finite fields of a special form which are very useful for software implementation of elliptic curve cryptosystems. Bailey and Paar introduced efficient OEF arithmetic algorithms including the $p^ith$ powering operation, and an efficient algorithm to construct OEFs for cryptographic use. In this paper, we give a counterexample where their $p^ith$ powering algorithm does not work, and show that their OEF construction algorithm is faulty, i.e., it may produce some non-OEFs as output. We present improved algorithms which correct these problems, and give improved statistics for the number of OEFs.

• Journal of applied mathematics & informatics
• /
• v.32 no.1_2
• /
• pp.17-26
• /
• 2014

In this paper, we present an algorithm for computing the number of points on the Jacobian varieties of genus 3 hyperelliptic curves of type $y^2=x^7+ax$ over finite prime fields. The problem of determining the group order of the Jacobian varieties of algebraic curves defined over finite fields is important not only arithmetic geometry but also curve-based cryptosystems in order to find a secure curve. Based on this, we provide the explicit formula of the characteristic polynomial of the Frobenius endomorphism of the Jacobian variety of hyperelliptic curve $y^2=x^7+ax$ over a finite field $\mathbb{F}_p$ with $p{\equiv}1$ modulo 12. Moreover, we also introduce some implementation results by using our algorithm.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.4 no.3
• /
• pp.197-203
• /
• 2009

Finite field arithmetic is very important in the area of cryptographic applications and coding theory, and it is efficient to use normal bases in hardware implementation. Using the fact that $GF(2^{mk})$ having a type-I optimal normal basis becomes the extension field of $GF(2^m)$, we, in this paper, propose a new serial multiplier which reduce the critical XOR path delay of the best known Reyhani-Masoleh and Hasan's serial multiplier by 25% and the number of XOR gates of Kwon et al.'s multiplier by 2 based on the Reyhani-Masoleh and Hasan's serial multiplier for type-I optimal normal basis.

• ETRI Journal
• /
• v.35 no.3
• /
• pp.523-529
• /
• 2013

Subquadratic space complexity multipliers for optimal normal bases (ONBs) have been proposed for practical applications. However, for the Gaussian normal basis (GNB) of type t > 2 as well as the normal basis (NB), there is no known subquadratic space complexity multiplier. In this paper, we propose the first subquadratic space complexity multipliers for the type 4 GNB. The idea is based on the fact that the finite field GF($2^n$) with the type 4 GNB can be embedded into fields with an ONB.

• Journal of IKEEE
• /
• v.22 no.3
• /
• pp.522-531
• /
• 2018

A public-key cryptography processor EC-RSA was designed, which integrates a 224-bit prime field elliptic curve cryptography (ECC) defined in the FIPS 186-2 as well as RSA with 2048-bit key length into a single hardware structure. A finite field arithmetic core used in both scalar multiplication for ECC and exponentiation for RSA was designed with 32-bit data-path. A lightweight implementation was achieved by an efficient hardware sharing of the finite field arithmetic core and internal memory for ECC and RSA operations. The EC-RSA processor was verified by FPGA implementation. It occupied 11,779 gate equivalents (GEs) and 14 kbit RAM synthesized with a 180-nm CMOS cell library and the estimated maximum clock frequency was 133 MHz. It takes 867,746 clock cycles for ECC scalar multiplication resulting in the estimated throughput of 34.3 kbps, and takes 26,149,013 clock cycles for RSA decryption resulting in the estimated throughput of 10.4 kbps.