• 마이크로전자및패키징학회지
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• 제31권1호
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• pp.35-42
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• 2024

최근 반도체 칩의 소형화 및 고집적화에 따라 미세 피치에 의한 범프 브리지 (bump bridge) 현상이 문제점으로 주목받고 있다. 이에 따라 범프 브리지 현상을 최소화할 수 있는 Cu pillar bump가 미세 피치에 대응하기 위해 반도체 패키지 산업에서 널리 적용되고 있다. 고온의 환경에 노출될 경우, 접합부 계면에 형성되는 금속간화합물(Intermetallic compound, IMC)의 두께가 증가함과 동시에 일부 IMC/Cu 및 IMC 계면 내부에 Kirkendall void가 형성되어 성장하게 된다. IMC의 과도한 성장과 Kirkendall void의 형성 및 성장은 접합부에 대한 기계적 신뢰성을 약화시키기 때문에 이를 제어하는 것이 중요하다. 따라서, 본 연구에서는 CS(Cu+ Sn-1.8Ag Solder) 구조 Cu pillar bump의 등온 시효 처리에 따른 접합부 특성 평가가 수행되었으며 그 결과가 보고되었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.24-24
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• 2009

ENIG(Electroless Nickel Immersion Gold) is the surface treatment method that is used most widely at fine pitch's SMT and BGA packaging process. In this paper, we have studied the effect of P content variation during ENIG process on those phenomena related to the solder joint. The effect of P content was discussed using the results obtained from FE-SEM, EPMA, EDS and FIB. Finally, it was concluded that the more P-content in Ni layer, the thicker P-rich layer.

• 마이크로전자및패키징학회지
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• 제19권3호
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• pp.15-20
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• 2012

In electronics industry, the coming electronic devices will be expected to be high integration and convergence electronics. And also, it will be expected that the coming electronics will be flexible, bendable and wearable electronics. Therefore, the demands and interests of bonding technology between flexible substrate and chip for mobile electronics, e-paper etc. have been increased because of weight and flexibility of flexible substrate. Considering fine pitch for high density and thermal damage of flexible substrate during bonding process, the micro solder bump technology for high density and low temperature bonding process for reducing thermal damage will be required. In this study, we researched on bonding technology of chip and flexible substrate by using 25um Cu pillar bumps and Sn-Bi solder bumps were formed by electroplating. From the our study, we suggest technology on Cu pillar bump formation, Sn-Bi solder bump formation, and bonding process of chip and flexible substrate for the coming electronics.

• 마이크로전자및패키징학회지
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• 제27권1호
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• pp.17-24
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• 2020

As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to fine-pitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO₂ hybrid bonding.

• Journal of Welding and Joining
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• 제33권3호
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• pp.47-53
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• 2015

By the trends of electronic package to be more integrative, the fine Cu trace pitch of organic PCB is required to be a robust design. In this study, the short circuit failure mechanism of PCB with a Cl element under the Temperature humidity bias test ($85^{\circ}C$/85%RH/3.5V) was examined by micro-structural study. A focused ion beam (FIB) and an electron probe micro analysis (EPMA) were used to polish the cross sections to reveal details of the microstructure of the failure mode. It is found that $CuCl_x$ were formed and grown on Cu trace during the $170^{\circ}C$/3hrs and that $CuCl_x$ was decomposed into Cu dendrite and $Cl_2$ gas during the $85^{\circ}C$/85%RH/3.5V. It is suggested that Cu dendrites formed on Cu trace lead to a short circuit failure between a pair of Cu traces.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 International Symposium
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• pp.21-30
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• 2002

According the difference of flex substrate, (reel tape), there are three kind assembly types of LCD driver IC is COG, TCP and COF, respectively. The TCP is the maturest in these types for stability of raw material supply and other specification. And TCP is the major assembly type of LCD driver IC and the huge demand from Taiwan's large TFT LCD panel house since this spring. But due to its package structure and the raw material applied in this package, there is some limitation in fine pitch application of this package type, (TCP). So, COF will be very potential in compact and portable application comparison with TCP in the future. There are three kinds assembly methods in COF, one is ACF by using the anisotropic conductive film to connect the copper lead of tape and gold bump of IC, another is eutectic bonding by using the thermo-pressure to joint the copper lead of tape and gold bump of IC, and last is NCP by using non-conductive paste to adhere the copper lead of tape and gold bump of IC. To have a global realization, this paper will briefly review the status of Taiwan's large TFT panel house, the internal driver IC design house, and the back-end assembly house in the beginning. The different material property of raw material, PI tape is also compared in the paper. The more detail of three kinds of COF assembly method will be described and compared in this paper.

• Design & Manufacturing
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• 제10권3호
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• pp.1-7
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• 2016

In the semiconductor industry the memory and chip were developed to high density memory and high performance chip, so circuit design was also high integrated and the test bed was needed to be thin and fine pitch socket. LGA(Land Grid Array) IC socket with thin wall thickness was designed to satisfy this requirement. The LGA IC socket plastic part was manufacture by injection molding process, it was needed accuracy, stiffness and suit resin with high flowability. After injection molding process the side gates were needed to remove for further assembly process. ln this study, the cold press cutting process was applied to remove the gates. For design of punch and die, the cold press cutting analysis was implemented by$DEFORM-2D^{TM}$ ln consideration of the simulation results, an adequate punch and die was designed and made for the cutting unit. In order to verify the performance of cutting process, the roughness of cutting section of the part was measured and was satisfied in requirement.

• 한국전기전자재료학회논문지
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• 제21권3호
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• pp.265-271
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• 2008

TCP(Tape Carrier Package), COG (Chip On Glass), COF(Chip On Film) are three methods for connecting LDI(LCD Driver IC) with LCD panels. Especially COF is growing its portion of market place because of low cost and fine pitch correspondence. But COF has a problem of the lead broken failure in LCD module process and the usage of customer. During PCB (Printed Circuit Board) bonding process, the mismatch of the coefficient of thermal expansion between PCB and D-IC makes stress-concentration in COF lead, and also D-IC bending process during module assembly process makes the level of stress in COF lead higher. As an affecting factors of lead-broken failure, the effects of SR(Solder Resister) coating on the COF lead, surface roughness and grain size of COF lead, PI(Polyimide) film thickness, lead width and the ACF(Anisotropic Conductive Film) overlap were studied, The optimization of these affecting manufacturing processes and materials were suggested and verified to prevent the lead-broken failure.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.457-457
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• 2000

The display module of PDP consists of a pair of fine electrode patterned panels. For example, in case of 42" PDP, thousands of electrode patterns should be placed on panel, where length, width, and height of each pattern m one meter, 50${\mu}{\textrm}{m}$, and 30${\mu}{\textrm}{m}$ respectively. And pitch between patterns is around 200${\mu}{\textrm}{m}$. Electrode patterns are frequently damaged during the production process, and thus might be broken. These breakage will result in open-circuited electrical characteristic of a pattern and/or open-circuited electrical characteristic between patterns. Therefore, inspection of pattern defects is the inevitable process to improve production yield rate of the panel. In this paper, we first review several types of PDP pattern defects which affects yield-rate of PDP. And, problems of inspecting such pattern defects by a typical inspection method is addressed. Then, a novel inspection method is proposed to overcome the difficulties, where some new components and the algorithm to detect the electrode defects are explored.ored.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2015년도 추계학술대회 논문집
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• pp.33-42
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• 2015

오늘날 연성회로기판(FCCL : Flexible Copper Clad Laminate)은 디스플레이, 스마트폰, 자동차, 항공, 의료 기기, 산업용 컨트롤 기기 등 거의 모든 고급 전자 제품들에 사용되고 있다. 특히 디스플레이 분야에서는 뛰어난 연성과 내구성을 바탕으로 경박단소화에 유리할 뿐만 아니라 구동부에 적용이 가능한 장점 등으로 그 적용처가 점점 늘어나고 있는 추세이다. 이 가운데서도 LCD와 OLED의 구동소자(Display Driver IC)를 장착하는 COF(Chip on Film)는 대표적인 연성회로기판(FCCL) 적용 부품으로서, 최근 인기를 끌고 있는 디스플레이의 제로-베젤(Zero-bezel)을 가능케 하는 핵심 부품이다. COF용 연성회로기판(FCCL) 소재로는 우수한 평탄도, 파인피치(Fine-pitch)구현성, 내굴곡성, 광투과성 등을 보유하고 있는 Sputtering Type FCCL이 사용되고 있다. 특히 최근 Display 분야의 화두가 되고 있는 POLED(Plastic-OLED) 패널을 장착한 Flexible Mobile 디스플레이의 경우, 기존의 COG(Chip on Glass) 접합방식이 아닌 COF 접합방식을 채택하고 있으며, 기존의 단면 COF보다 3배의 고해상도 구현이 가능한 양면 COF를 채택하기에 이르렀다. 기존의 COF 제작공정과 달리 Semi Additive 공정으로 제작되는 양면 COF 시장의 태동으로 양면 연성회로기판(FCCL)의 수요 증가가 예상되는 등 최근 디스플레이 기술 발전은 소재 분야에도 큰 변화를 잉태하고 있다. 이러한 최근 디스플레이 업계의 고해상도, 고속 신호 전송, 슬림화, Flexible 추세에 대응 가능한 최적의 특성을 보유하고 있는 Sputtering Type FCCL을 중심으로 디스플레이의 발전에 대응하는 소재의 기술 개발 동향을 살펴보고자 한다.