• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1597-1609
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• 2015

This paper introduces the fundamentals of the conventional LC low-pass filter circuit in the fractional domain. First, we study the new fundamentals of fractional-order LC low-pass filter circuit including the pure real angular frequency, the pure imaginary angular frequency and the short circuit angular frequency. Moreover, sensitivity analysis of the impedance characteristics and phase characteristics of the LC low-pass filter circuit with respect to the system variables is studied in detail, which shows the greater flexibility of the fractional-order filter circuit in designs. Furthermore, from the filtering property perspective, we systematically investigate the effects of the system variables (LC, frequency f and fractional orders) on the amplitude-frequency characteristics and phase-frequency characteristics. In addition, the detailed analyses of the cut-off frequency and filter factor are presented. Numerical experimental results are presented to verify the theoretical results introduced in this paper.

• 조명전기설비학회논문지
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• 제29권6호
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• pp.78-89
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• 2015

Conventional EMI filters have tried to use an active EMI filter as a series by the series connection of two EMI filters for CM and DM noise. However, the proposed filter is formed into one circuit by using the active EMI filter which is able to filter CM and DM noise components together. As a result, the active EMI filter showed the outstanding quality in mass and volume under 50% and electric characteristics have been compared to the passive EMI filter in approximately 150kHz~10MHz. Furthermore, the proposed circuit has simple circuit components by comparing with the series EMI filters, and electrical characteristics are similar. The noise have been attenuated to maximum 20dBuV.

• 한국통신학회논문지
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• 제24권9A호
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• pp.1434-1441
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• 1999

본 논문에서는 Hairpin Line 여파기의 정확한 해석 및 설계를 위한 등가회로를 제시하였으며 제시된 등가회로의 유효성을 컴퓨터 시뮬레이션과 설계를 통해 입증하였다. Hairpin Line 여파기에 대한 설계식은 다양하게 제시되었으나, 인접하지 않는 소자간의 상호 연결성을 포함한 실제적으로 간단화된 등가회로는 아직 명시되고 있지 못하다. 본 논문에서는 회로 duality을 이용하여 Hairpin Line 여파기 회로의 모든 개방단자를 단락단자로 변환하고, 변환된 회로를 그래프 모델로 표시하였다. 또한 각 단자에서의 경계조건으로부터 보다 간략화된 회로모델을 구하고 역 dual구조로 변환하여 Hairpin Line 여파기에 대한 간단화된 등가회로를 유도하였다.

• 전기학회논문지
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• 제57권11호
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• pp.2127-2130
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• 2008

In this paper, a tunable bandpass filter with mutual inductive coupling circuits is newly designed and demonstrated for UHF TV tuner ranged from Ch.14(473MHz) to Ch.69(803MHz) applications. Conventional HF tuning circuit with an electromagnetic bandpass filter has several problems such as large size, high volume and high cost, since the electromagnetic filter is comprised of several passive components and air core inductors to be assembled and controlled manually. To address these obstacles, peaking chip inductor was newly applied for constructing the mutual inductive coupling circuit. The proposed circuit was newly and optimally designed, since the chip inductor showed lower components Q-value than the air core inductor. A varactor diode has been also used to fabricate the proposed tunable bandpass filter for RF tuning circuit. The fabricated tunable filter exhibited low insertion loss of approximately -3dB, high return loss of below -10dB, and large tuning bandwidth of 330MHz.

• 한국산학기술학회논문지
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• 제9권5호
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• pp.1172-1177
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• 2008

채널 선택용 필터의 전압오차를 보정하기 위해 전류비교 방식의 전압안정화 회로를 설계하였다. 제안된 전류비교 방식의 전압안정화 회로는 부속회로를 첨가 할 필요가 없어 칩 면적을 최소화 할 수 있고 저전압 저전력용 채널 선택용 필터 설계에 매우 유용하다. 제안된 안정화 회로의 응용 회로로써 블루투스 통신 시스템 채널을 포함한 3개의 통신채널을 이용하였다. $0.18{\mu}m$ CMOS 공정파라메터를 사용하여 HSPICE 시뮬레이션 한 결과, 제안된 안정화 회로는 3개의 통신 채널에서 각각 $12{\mu}s$, $13{\mu}s$, $15{\mu}s$이내에서 동작할 수 있음을 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.514-517
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• 1998

This paper proposed a symmetric feedback current enhancement circuit with 1.5V power supply to design a 3$^{rd}$ order butterworth low pass filter. The proposed filter designed on 0.8.mu.m CMOS n-well double poly/double metal process simulated in HSPICE composed of the 3dB frequency enhancement circuit and the unity-gain frequency enhancement circuit. The simulation result on the design filter shows the badnwith of 25MHz, phase of 92.6 .deg. and power consumption of 0.3mW..

• Journal of electromagnetic engineering and science
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• 제2권2호
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• pp.100-104
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• 2002

A proper equivalent circuit model for coupling iris has been derived in order to compensate the length of cavity in a $TE_{011}$TEX> mode cylindrical cavity filter. A method to resolve the difference in bandwidth and feature or ripple systematically has been proposed. This method can be applied to other types of waveguide cavity filter.

• 전기학회논문지
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• 제59권5호
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• pp.1005-1009
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• 2010

This paper presents a digitally-controlled filter calibration technique for biquad RC filter using self oscillation. The biquad RC filter is converted to a fully-differential ring oscillator by changing its resistor connections, where the oscillation frequency reflects the cut-off frequency. The proposed calibration circuit measures the oscillation frequency by counting with a fixed higher-frequency clock and then tunes it to a desired frequency with a digital frequency-locked loop including a PI controller. Because the proposed circuit directly measures the cut-off frequency of the filter itself and calibrates it with the small area digital circuits, the area and the power consumption are much small compared with conventional works. When it is implemented in a 65nm CMOS process, the calibration circuit except the filter consumes the area of 80um X 50um and power consumption is 443uA at 1.2 V supply voltage.

• 한국전기전자재료학회논문지
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• 제13권7호
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• pp.583-591
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• 2000

It this paper the multilayer chip band pass filter for next generation mobile communication phone is fabricated and designed. For the design the multilayer chip filter of non-contented equivalent circuit and contented equivalent circuit with attenuation pole is presented. Finally it is fabricated and designed using the multilayer chip filter of contented equivalent circuit with attenuation pole. The size insertion loss center frequency and band width of multilayer chip filter are 4.5$\times$3.2$\times$2.0[mm], 3.0[d.B] and 1945$\pm$25 MHz respectively. The multilayer chip filter was fabricated by screen printing with Ag electrode after tape casting. Simulation results of multilayer chip filter are compared with experimental results and found to be in excellent agreements.

• 전력전자학회논문지
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• 제13권1호
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• pp.63-69
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• 2008

구형파 BLDC (Brushless DC) 전동기를 구동시키기 위해서는 전동기의 회전자 위치에 대한 정보를 아는 것이 필수적이다. 본 논문에서는 회전자 위치를 검출하기 위해 일반적으로 사용되는 홀센서나 엔코더를 이용하지 않고 각상을 저항으로 Y결선하여 만들어지는 단자의 전압에 포함되어 있는 역기전력을 클램프 회로를 통한 필터회로를 이용하여 전동기의 회전자 위치를 검출하는 구형파 BLDC 전동기를 위한 센서리스 드라이브 시스템을 제안한다. 특히 본 논문에서 제안한 새로운 역기전력 증폭 제한 회로를 통한 필터회로를 구성하여 저속영역에서 센서리스를 특성을 개선하였다. 그리고 이를 실제로 100[W]급 BLDC 구동용 프로토 타입 드라이브를 제작하여 제안된 역기전력 증폭 제한 회로의 타당성 검증하였다.