• Journal of Korean Society for Geospatial Information Science
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• v.17 no.3
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• pp.13-21
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• 2009

Digital map should have the up-to-dateness as well as the accuracy to perform a role as the national spatial data. As digital mapping process require aerial photograph, surveying, and field working, it consumes a lot of time and cost. So there is a limit to maintain the up-to-dateness. If we updates the digital map frequently by using the as-built drawings, we can prevent the waste of national budget by reuse of existing drawings and make accuracy updates from existing survey results. In spite of this advantages, due to insufficiency of CAD drawing standard, inconsistency of file types of as-built drawings and digital maps, and topology relations between input features and original features, so the frequent updates using the as-built drawings is on the difficult situation to perform. In this research, first, CAD features extracted from as-built drawings land the new/update whether original features exist or not and generate topology from spatial relation of features. Second, suggest the efficient partial-update-plan performing integrity test. As a result, guarantee the accuracy and the up-to-dateness of digital map.

• Restorative Dentistry and Endodontics
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• v.22 no.2
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• pp.648-658
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• 1997

The purpose of this study was to compare the effects of various techniques on the quality and quantity of instrumentation in curved canals. Instrumentation time was evaluated too. Forty eight canals of resin blocks($35^{\circ}$) were divided into three groups and filed. In group A, 16 blocks were instrumented using a step-back technique with stainless steel(SS) K-file(Mani, Matsutani Seisakusho Co.,Japan). In group B, canals were prepared with SS K-files using the Endo-Angle (Nakanishi Dental MFG.CO.,LTD.,Japan). Group C was prepared using N i-Ti engine-driven instruments (Quantec Series $2000^{TM}$ system). Group A and B were filed from # 5 to # 25 at the apex followed by a 1 mm stepback technique, and the coronal half of the canals were flared with Gates Glidden burs(#2,3,4). Group C was instrumented from # 1 to # 8. After the instrumentation time was measured, canals were filled with India ink, and photographed, which to magnify the canal images 8 times. Using these photographs the apical portions were evaluated And scored from 1 to 4 according to the severity of ledging and zipping. On the same photographs, the area of the coronal two thirds of the canals were measured using a personal computer with the computer program Brain and Digitizer (SummaSketch III). The following results were obtained. 1. Instrumentation time was significantly shorter for group C, as opposed to group A and B(ANOVA, P<0.05). 2. The qualitative evaluation of the apical portions of the canals showed no significant difference between the groups(Kruscal-Wallis, p>0.05). 3. The area removed by group C was significantly smaller than group A and B(ANOVA, P<0.05).

• The Journal of the Korea Contents Association
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• v.10 no.12
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• pp.70-76
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• 2010

This paper Extended ELZW(EBCDIC Lempel Ziv Welch) algorithm uses 2 byte prefix field for pointer of a table and 1 byte suffix field for repeat counter. where, a prefix field uses a pointer(index) of compression table and a suffix field uses a counter of overlapping or recursion text data in compression table. To increase compression ratio, after construction of compression table, table data are properly packed as different bit string in accordance with a alphabet, Hangeul, and pointer respectively. Therefore, proposed ELZW algorithm is superior to 1byte LZW algorithm as 5.22 percent and superior to 2byte LZW algorithm as 8.96 percent.

• Journal of Information Processing Systems
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• v.15 no.6
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• pp.1277-1295
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• 2019

With its technical development, digital printing is being universally introduced to the mass production of clothing factories. At the same time, many fashion platforms have been made for customers' participation using digital printing, and a tool is provided in platforms for customers to make designs. However, there is no sufficient solution in the production stage for automatically converting a customer's design into a file before printing other than designating a square area for the pattern designed by the customer. That is, if 30 different designs come in from customers for one shirt, designers have to do the work of reproducing the design on the clothing pattern in the same location and in the same angle, and this work requires a great deal of manpower. Therefore, it is necessary to develop a technology which can let the customer make the design and, at the same time, reflect it in the clothing pattern. This is defined in relation to the existing clothing pattern with digital printing. This study yields a clothing pattern for digital printing which reflects a customer's design in real time by matching the diagram area where a customer designs on a given clothing model and the area where a standard pattern reflects the customer's actual design information. Designers can substitute the complex mapping operation of programmers with a simple area-matching operation. As there is no limit to clothing designs, the variousfashion design creations of designers and the diverse customizing demands of customers can be satisfied at low cost with high efficiency. This is not restricted to T-shirts or eco-bags but can be applied to all woven wear, including men's, women's, and children's clothing, except knitwear.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.79-90
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• 2000

In this paper, a high-performance floating point unit, which is suitable for high-performance superscalar microprocessors and supports IEEE 754 standard, is designed. Floating-point arithmetic unit (AU) supports all denormalized number processing through hardware, while eliminating the additional delay time due to the denormalized number processing by proposing the proposed gradual underflow prediction (GUP) scheme. Contrary to the existing fixed-radix implementations, floating-point divide/square root unit adopts a new architecture which determines variable length quotient bits per cycle. The new architecture is superior to the SRT implementations in terms of performance and design complexity. Moreover, sophisticated exception prediction scheme enables precise exception to be implemented with ease on various superscalar microprocessors, and removes the stall cycles in division. Designed floating-point AU and divide/square root unit are integrated with and instruction decoder, register file, memory model and multiplier to form a floating-point unit, and its function and performance is verified.

• The Journal of Society for e-Business Studies
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• v.15 no.4
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• pp.21-31
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• 2010

Recently e-business such as online financial trade and online shopping using mobile computes are widely spread. Most of mobile computers use NAND flash memory-based storage devices for storing data. Flash memory storage devices use a software called flash translation layer to translate logical address from a file system to physical address of flash memory by using mapping tables. The legacy FTLs have a problem that they must maintain very large mapping tables in the RAM. In order to address this issues, in this paper, we proposed a new caching scheme of mapping tables. We showed through the trace-driven simulations that the proposed caching scheme reduces the space overhead dramatically but does not increase the time overhead. In the case of online transaction workload in e-business environment, in particular, the proposed scheme manifests better performance in reducing the space overhead.

• The Journal of Society for e-Business Studies
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• v.15 no.4
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• pp.101-121
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• 2010

This paper presents an intelligent prefetching technique that significantly improves performance of hybrid fash-disk storage, a combination of flash memory and hard disk. Since flash memory embedded in a hybrid device is much faster than hard disk in terms of I/O operations, it can be utilized as a 'cache' space to improve system performance. The basic strategy for prefetching is to utilize sequential pattern mining, with which we can extract the access patterns of objects from historical access sequences. We use two techniques for enhancing the performance of hybrid storage with prefetching. One of them is to modify a FAST algorithm for mapping the flash memory. The other is to extend the unit of prefetching to a block level as well as a file level for effectively utilizing flash memory space. For evaluating the proposed technique, we perform the experiments using the synthetic data and real UCC data, and prove the usability of our technique.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.99-114
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• 2000

In the secure DNS the amount of information that should be managed greatly increased and the interdependency in the information became very complex. Therefore, it became necessary to develop a mechanism which can manage zone information efficiently. Moreover, a consistent interface became also necessary so that a secure DNS may be efficiently interconnected with other Internet application services. In this paper we explain the design and implementation of a secure DNS extended with two functions : (1) a dynamic update function which enables to add and remove zone information dynamically and (2) a zone transfer function that efficiently transfers update zone information among DNS servers. We developed a method which integrates two zone transfer mechanisms, full zone transfer and incremental zone transfer, and also proposed a method to compress data in the zone transfer message. We also introduced a data structure called a delta file to integrate the zone transfer function and the dynamic update function.

• The KIPS Transactions:PartD
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• v.8D no.3
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• pp.273-284
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• 2001

A systematic approach for interpreting Korean addresses based on postal code is presented in this paper. The implementation is focused on producing the final delivery point code from various types of address recognized. There are two stages in the address interpretation : 1) agreement verification between the recognized postal code and upper part of the address and 2) analysis of lower part of the address. In the agreement verification procedure, the recognized postal code is used as the key to the address dictionary and each of the retrieved addresses is compared with the words in the recognized address. As the result, the boundary between the upper part and the lower part is located. The confusion matrix, which is introduced to correct possible mis-recognized characters, is applied to improve the performance of the process. In the procedure for interpreting the lower part address, a delivery code is assigned using the house number and/or the building name. Several rules for the interpretation have been developed based on the real addresses collected. Experiments have been performed to evaluate the proposed approach using addresses collected from Kwangju and Pusan areas.

• The KIPS Transactions:PartA
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• v.13A no.6 s.103
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• pp.517-524
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• 2006

In cluster computers, it is essential to Implement the single I/O space(SIOS) supporting integrated I/O substructure to efficiently process I/O intensive applications. SIOS service provides with global I/O address space to directly access peripherals and hard disks in its own or remote nodes from any node in the cluster computer In this thesis, we propose the implementation method of SIOS in Linux clusters by using only freewares. This method is implemented at device driver level that uses Enhanced Network Block Device(ENBD) and file system level that uses S/W RAID and NFS. The major strengths of this method are easiness of implementation and almost no cost due to using freewares. In addition, since freewares used are open sources, it is possible to apply this method to other platforms with only slight modification. Moreover, experiments show that I/O throughputs are up to 5.5 times higher in write operations and approximately 2.3 times higher in read operations than those of CDD method that uses the device driver developed at kernel level.