• 한국멀티미디어학회논문지
• /
• 제9권12호
• /
• pp.1681-1688
• /
• 2006

GIS systems have gradually been utilized in life information as well as special businesses such as traffic, sight-seeing, tracking, and disaster services. Most GIS services focus on showing stored information on maps, not providing a service to register and modify their preferred information. In this paper, we present a new method which reduces DXF map data into Simple Geographic Information File format using format conversion algorithms. We also present the prototype implementation of a GIS search system based on ontologies to support associated information. Our contribution is to propose a new digital map format to provide a fast map loading service and individual customized information on the map service.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2004년도 학술대회 논문집 전문대학교육위원
• /
• pp.120-122
• /
• 2004

This paper describes the digital relay simulator by use of DSP for digital relay test. The simulator software has EMTP simulation data file conversion. user define simulation data generation. data analysis engine. etc. The simulator hardware design uses 32bit floating point DSP architecture to achivev flexibility and high speed operation.

• 한국공작기계학회논문집
• /
• 제11권1호
• /
• pp.61-69
• /
• 2002

This paper describes a converting algorithm between programmable languages of a software PLU. It is based on IEC 61131-3 standard and PC. The proposed control logic is designed by the software model and common element with data type, variables, POUs(program organization unit) and execution control unit commonly used within programmable languages of IEC 61131-3 Standard. The generation method of object file is proposed on five programmable language based on IEC 61131-3. It is represented as fo11ows; 1) the generation method using conversion algorithm from LD to IL with FBD(function block diagram), 2) the generation method using f code generation algorithm from SFC using the SFC execution sequence with FBD and ST(structured text). The proposed control logic generator was implemented by Visual C++ 6.0 and MFC on MS-windows NT 4.0.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
• /
• pp.105-108
• /
• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

• 대한임베디드공학회논문지
• /
• 제10권6호
• /
• pp.345-352
• /
• 2015

Recently, by developing many training systems in battle field, the demand for interconnecting and internetworking between Live, Virtual, Constructive training systems has been increased to support efficient data distribution and system control. But, there are lots of problems for them to interwork, because the existing researches only support L-L, V-V, C-C Interoperability. Therefore, we propose L-V-C gateway to provide interoperable simulation environment based on HLA and DDS between them. First, we illustrate FOM Management that parses RPR-FOM XML file to acquire Data information to be shared between them, and generates common data structure and source code used for L-V-C Gateway. L-V-C Gateway created from FOM Management supports Data Conversion and Quality of Service between HLA and DDS. HLA Federate and DDS Domainparticipant in L-V-C Gateway play a role of logical communication channel and relay data from HLA Federation to DDS Domain and vice versa.

• 한국군사과학기술학회지
• /
• 제14권4호
• /
• pp.607-614
• /
• 2011

This paper describes the development of pulse code modulation(PCM) data recorder with design, implementation and environmental test. PCM serial data that diverged from telemetry encoder output is used as the input and is reformed to parallel signal through FPGA processing. Controllers construct the packet by the sector and record it into non-volatile memory. Compact flash(CF) memory for data storage media, USB interface for data downloading, and a software for operating status diagnosis and file format conversion are used.

• 전기학회논문지P
• /
• 제55권4호
• /
• pp.183-189
• /
• 2006

In this work, the digital simulator for testing of digital protective relay is presented. The proposed simulator software has EMTP simulation data file conversion, sequence waveform generation, user define simulation data generation, communication engine, data analysis engine and measurements function etc. The simulator hardware is designed using 32bit floating point DSP architecture to achieve flexibility and high speed operation. This simulator is tested to evaluate the performance of relay simulator by using a output data of simulation model on EMTP.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2001년도 하계학술대회 논문집 A
• /
• pp.237-239
• /
• 2001

This paper describes the digital relay simulator system using digital signal processor. The simulator system has two parts, one is software and the other is hardware part. The simulation software has variety calculation engines ; EMTP simulation data file conversion, user define simulation data generation, sequence data generation, data analysis engines. etc, these are designed upon GUI. And simulator software provides easy control interface for users, the simulator software performs on every MS Windows OS. The simulator hardware design uses 32bit floating point DSP(TMS320C32) architecture to achieve flexibility and high speed operation.

• ETRI Journal
• /
• 제37권6호
• /
• pp.1055-1064
• /
• 2015

We demonstrate a next-generation high-capacity mobile fronthaul based on radio over fiber (RoF) technology, which links between a digital unit and a radio unit supporting two frequency assignments and $2{\times}2$ multiple input, multiple output antennas. To confirm the technical feasibility of a mobile fronthaul, we experimentally investigate its down- and uplink end-to-end performances including the optical and radio frequency (RF) signal path. Frequency-dependent performance deviations, error vector magnitude variations, overall system performance variations caused by optical to electrical conversion, and intermediate frequency to RF conversions are examined. Experimental verifications on multiple LTE uplink signals are performed for the first time. We also demonstrate several commercial mobile Internet services, YouTube video streaming, and file transfers using off-the-shelf mobile devices, through a mobile fronthaul based on RoF.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2003년도 하계학술대회 논문집 A
• /
• pp.393-395
• /
• 2003

This paper deals with the monitoring program based on Windows for Distribution Panel Tester. The monitoring software has variety function : data file conversion, user define data generation, data metering and signal analysis etc. The software is designed for GUI because it provides easy test and control interface for users or operators.