• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.35 no.6
• /
• pp.556-563
• /
• 2007

The current trend of low cost ultra-small satellites is to utilize Commercial Off the Shelf (COTS) parts to save cost, and accordingly, Command and Data Handling (C&DH) that operates the satellite and collects/processes the data is also designed and developed around commercial controllers. However, functionalities of commercial controllers are limited according to the specs outlined by the manufacturer. In order for the commercial controllers to be used for satellites where variety of interfaces is required, a separate interface circuit is required. Therefore, a Multi Digital Data Control System (MDDCS) using Field Programmable Gate Array (FPGA) has been developed in order to expand multiple digital interfaces that are not supported by the commercial controller, and also to compensate for SEU. This has been implemented on Actel A3P1000 using Very High Speed Integrated Circuits Hardware Description Language (VHDL).

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.11C
• /
• pp.1102-1110
• /
• 2007

In this paper, we design the FPGA (Field-Programmable Gate Array) of the CAMB (Constant-Amplitude Multi-code Biorthogonal) modulation, and implement the SoC (System on Chip). The ASIC (Application Specific Integrated Circuit) chip is be implemented through targeting and board test. This 12Mbps modem SoC includes the ARM (Advanced RISC Machine)7TDMI, 64Kbyte SRAM(Static Random Access Memory) and ADC (Analog to Digital Converter)/DAC (Digital to Analog Converter) for flexible applications. Additionally, the modem SoC can support the variable communication interfaces such as the 16-bits PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus) 1.1, and 16C550 Compatible UART (Universal Asynchronous Receiver/Transmitter).

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.4
• /
• pp.193-200
• /
• 2014

In this paper, the prototype of one-channel gamma-ray spectroscope for automatic radiopharmaceutical systhesis system was designed and characterized. The prototype employed CZT (CdZnTe) spear detector for gamma-ray detection and employed analog-type signal processing method. A radioactive sample Co-60 was used for measuring performance of the gamma-ray spectroscope and energy spectrum is gained with bandwidth of 1173keV. The analog board is made up of SF (shaping filter) and PHA (peak and hold amplifier) for shaping CZT output signal appropriately and ADC (analog to digital converter) and FPGA (field programmable gate array) for drawing gamma-ray spectrum by counting the digitalized gamma-ray signal data.

• Journal of IKEEE
• /
• v.20 no.4
• /
• pp.344-350
• /
• 2016

In this Paper, we propose an optimized method of hardware design based on Field Programmable Gate Array (FPGA) to detect rotated angle of high definition image about Extreme Contour Point (ECP) algorithm with moving video image could be not happened to translation motion, but also physical rotation motion. It was evaluated by XC7Z020 xc7z020-3clg400 FPGA board by using xilinx 14.2 tool. The much well-known method, the Coordinate Rotation Digital Integrated Computation (CORDIC) is an algorithm to estimate rotated angle between point and point. Through the result both ECP and CORDIC, our proposed design are confirmed to have similar operating speed of about 4ns with CORDIC. However, it is verified to have high performance result in terms of the hardware cost, is much better than CORDIC with cost reduction of registers and Look Up Tables (LUTs) of 108% and 91%, respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.17 no.6
• /
• pp.161-167
• /
• 2017

Recently, small radar has been reduced in size and power consumption to cope with various operating environments. It also requires the development of a small millimeter wave radar with high range resolution to disable the system of target with a single strike. In this paper, we design and implement a signal processor that can be used in small millimeter wave radar. The signal processor for the small millmeter wave radar is designed with a digital IF(Intermediate Frequency) receiver and DFT(Discrete Fourier Transform) module capable of real time FFT operation for miniaturization and low power consumption. Also it was to leverage the FPGA(Field Programmable Gate Array) and DAC(Digital Analog Converter) as a means for correcting the distortion of signals that can occur in the receive path of the small millimeter wave radar to create a RF signal that is used by the system. Finally, we verified the signal processor presented through performance test

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.19 no.6
• /
• pp.79-85
• /
• 2019

Recently, small radar require the development of small millimeter wave radar with high distance resolution to disable the target's system with a single strike. Small millimeter wave radar with high distance resolution need to process large amounts of data in real time to acquire and track target. In this paper, we summarized the real-time data preprocessing method to process the large amount of data required for small millimeter wave radar. In addition, the digital IF(Intermediate Frequency) receiver, Window processing, and, DFT(Discrete Fourier Transform) functions presented by real-time data preprocessing are implemented using FPGA(Field Programmable Gate Array). Finally the implemented real-time data preprocessing module was applied to the signal processor for small millimeter wave radar and verified by performance test related to the real-time preprocessing function.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.46 no.4
• /
• pp.102-110
• /
• 2009

In this paper, we propose an object detection method for real-time in infrared (IR) images and PowerPC (PPC) and H/W design based on field programmable gate array (FPGA). An open H/W architecture has the advantages, such as easy transplantation of HW and S/W, support of compatibility and scalability for specification of current and previous versions, common module design using standardized design, and convenience of management and maintenance. Proposed background modeling for an open H/W architecture design decreases size of search area to construct a sparse block template of search area in IR images. We also apply to compensate for motion compensation when image moves in previous and current frames of IR sensor. Separation method of background and objects apply to adaptive values through time analysis of pixel intensity. Method of clutter reduction to appear near separated objects applies to median filter. Methods of background modeling, object detection, median filter, labeling, merge in the design embedded system execute in PFC processor. Based on experimental results, proposed method showed real-time object detection through global motion compensation and background modeling in the proposed embedded system.

• The Journal of the Acoustical Society of Korea
• /
• v.13 no.2E
• /
• pp.58-67
• /
• 1994

Hidden Markov Model (HMM)-based algorithms have been used successfully in many speech recognition systems, especially large vocabulary systems. Although general purpose processors can be employed for the system, they inevitably suffer from the computational complexity and enormous data. Therefore, it is essential for real-time speech recognition to develop specialized hardware to accelerate the recognition steps. This paper concerns with a real-time implementation of an isolated word recognition system based on HMM. The speech recognition system consists of a host computer (PC), a DSP board, and a prototype Viterbi scoring board. The DSP board extracts feature vectors of speech signal. The Viterbi scoring board has been implemented using three field-programmable gate array chips. It employs a hardware-efficient Viterbi scoring architecture and performs the Viterbi algorithm for HMM-based speech recognition. At the clock rate of 10 MHz, the system can update about 100,000 states within a single frame of 10ms.

• The Journal of the Acoustical Society of Korea
• /
• v.37 no.4
• /
• pp.215-222
• /
• 2018

This paper reports the development and performance evaluation of a backend system for real-time IVUS (Intravascular Ultrasound) imaging. The developed backend system was designed to minimize the amount of logic and memory usage by means of efficient LUTs (Look-up Tables), and it was implemented in a single FPGA (Field Programmable Gate Array) without using external memory. This makes it possible to implement the backend system that is less expensive, smaller, and lighter. The accuracy of the backend system implemented was evaluated by comparing the output of the FPGA with the result computed using a MATLAB program implemented in the same way as the VHDL (VHSIC Hardware Description Language) code. Based on the result of ex-vivo experiment using rabbit artery, the developed backend system was found to be suitable for real-time intravascular ultrasound imaging.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.10
• /
• pp.67-71
• /
• 2011

Existing face detection systems, which are used for digital door locks, digital cameras, video surveillance systems, and so on, are software-based implementation for relatively low level resolution images. Therefore, in this case, there are difficulties in detecting faces in a real-time fashion due to the increasing amount of operational processing as well as in allowing the requirements of face detections for HD(High Definition) resolutions. A hardware approach is necessary to efficiently find faces for HD images in real-time embedded systems. This paper proposes and implements a hardware architecture for an LBP(Local Binary Pattern) operation which is a time-consuming part as one of preprocessing steps for face detection. The hardware architecture proposed in this research has been implemented and tested with a FPGA(Field Programmable Gate Array) chip, and shown that the approach guarantees efficient face detection for HD images.