• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1C
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• pp.20-25
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• 2006

In this paper, the performance of Tree-LDPC code is presented based on the min-sum algorithm with scaling and the asymptotic performance in the water fall region is shown by density evolution. We presents that the Tree-LDPC code show a significant performance gain by scaling with the optimal scaling factor which is obtained by density evolution methods. We also show that the performance of min-sum with scaling is as good as the performance of sum-product while the decoding complexity of min-sum algorithm is much lower than that of sum-product algorithm. The Tree-LDPC decoder is implemented on a FPGA chip with a small interleaver size.

• ETRI Journal
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• v.25 no.5
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• pp.328-336
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• 2003

Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a $0.25-{\mu}m$ CMOS technology, the core size of which was only 2.79 $mm{\times}2.80mm$.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1787-1790
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• 2005

We have developed satellite devices for fine attitude control of the Science & Technology Satellite-2 (STSAT-2) scheduled to be launched in 2007. The analog sun sensors which have been continuously developed since the 1990s are not adequate for satellites which require fine attitude control system. From the mission requirements of STSAT-2, a compact, fast and fine digital sensor was proposed. The test of the fine attitude determination for the pitch and roll axis, though the main mission of STSAT-2, will be performed by the newly developed FDSS. The FDSS use a CMOS image sensor and has an accuracy of less than 0.01degrees, an update rate of 20Hz and a weight of less than 800g. A pinhole-type aperture is substituted for the optical lens to minimize the weight while maintaining sensor accuracy by a rigorous centroid algorithm. The target process speed is obtained by utilizing the Field Programmable Gate Array (FPGA) in acquiring images from the CMOS sensor, and storing and processing the data. This paper also describes the analysis of the optical performance for the proper aperture selection and the most effective centroid algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.261-267
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• 2001

This paper presents the architecture of multiple-queue manager for input-queued switch, which has arbitration latency, and the design of the chip. The proposed architecture of multiple-queue manager provides wire-speed routing with a pipelined buffer management, and the tolerance of requests and grants data transmission latency between the input queue manager and central arbiter using a new request control method, which is based on a high-speed shifter. The multiple-input-queue manager has been implemented in a field programmable gate array chip, which provides OC-48c port speed. It enhances the maximum throughput of the input queuing switch up to 98.6% with 128-cell shared input buffer in 16$\times$16 switch size.

• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.145-151
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• 2015

We describe in this paper a hardware-based improvement scheme of a real-time automatic speech recognition (ASR) system with respect to speed by designing a parallel feature extraction algorithm on a Field-Programmable Gate Array (FPGA). A computationally intensive block in the algorithm is identified implemented in hardware logic on the FPGA. One such block is mel-frequency cepstrum coefficient (MFCC) algorithm used for feature extraction process. We demonstrate that the FPGA platform may perform efficient feature extraction computation in the speech recognition system as compared to the generalpurpose CPU including the ARM processor. The Xilinx Zynq-7000 System on Chip (SoC) platform is used for the MFCC implementation. From this implementation described in this paper, we confirmed that the FPGA platform is approximately 500× faster than a sequential CPU implementation and 60× faster than a sequential ARM implementation. We thus verified that a parallelized and optimized MFCC architecture on the FPGA platform may significantly improve the execution time of an ASR system, compared to the CPU and ARM platforms.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.53 no.7
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• pp.365-374
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• 2004

The relay measures the frequency of the power system in order to detect faults and separate them from the system. Many estimation algorithms for the relay have been proposed to accurately measure the frequency. This paper proposes a new frequency measurement method using the digital phase locked-loop(DPLL) for the relay of the power system. The proposed method is configured with a DPLL scheme and verified through computer simulations and experimental tests. In order to cope with noises in the power system, filters are included in the input signal processing part and the frequency comparator. MATLAB is used for computer simulations and an experimental setup with a CPU and an FPGA(Field Programmable Gate Array) is constructed. The loop filter of the DPLL is run in the CPU software In adjust parameters and others are in the FPGA. Experimental tests are performed lot a function generator and the power system. Results show that the proposed method is appropriate to the frequency measurement for the relay.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.80-83
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• 2001

이족로봇이 stand-alone 형태를 가지기 위해서는 기계적인 구조가 중요할 뿐만 아니라 하드웨어시스템이 간결하게 잘 설계되어야 한다. 이렇게 하드웨어시스템이 가볍고 간결하여 설계되어야 쉽게 로봇에 장착할 수가 있다. 본 논문에서는 FPGA(Field Programmable Gate Array)를 이용해 모터 제어기를 구성해서 이족로봇을 설계하는 방법을 다루고자 한다. 본 논문에서 구성하는 하드웨어 시스템은 메인 CPU로 AM186ES를 사용하며 FPGA는 Altera사의 FLEX EPF10K20TC144-3을 사용하였다. 이와 같이 FPGA를 사용하는 하드웨어시스템은 기본적으로 VHDL언어를 사용하여 유연하게 하드웨어를 구성 할 수 있으며, 이족로봇의 여러 가지 보행 알고리즘에 능동적으로 대처할 수 있다. 뿐만 아니라 하드웨어가 간단해 지면서 가볍고 전력소모가 적으며 신뢰성 있는 시스템을 구축할 수 있다.

• Journal of IKEEE
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• v.23 no.4
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• pp.1400-1407
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• 2019

In this paper, we propose a support vector machine (SVM) based gas classifier that can support real-time self-learning. The modified sequential minimal optimization (MSMO) algorithm is employed to train the proposed SVM. By using a shared structure for learning and classification, the proposed SVM reduced the hardware area by 35% compared to the existing architecture. Our system was implemented with 3,337 CLB (configurable logic block) LUTs (look-up table) with Xilinx Zynq UltraScale+ FPGA (field programmable gate array) and verified that it can operate at the clock frequency of 108MHz.

• 제어로봇시스템학회:학술대회논문집
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• 1999.10a
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• pp.9-12
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• 1999

This paper presents the development of a control architecture for the autonomous underwater vehicle (AUV) with VARIVEC (variable vector) propeller. Moreover this paper also describes the new technique of controlling the servomotors using the Field Programmable Gate Array (FPGA). The AUVs are being currently used fur various work assignments. For the daily measuring task, conventional AUV are too large and too heavy. A small AUV will be necessary for efficient exploration and investigation of a wide range of a sea. AUVs are in the phase of research and development at present and there are still many problems to be solved such as power resources and underwater data transmission. Further, another important task is to make them smaller and lighter for excellent maneuverability and low power. Our goal is to develop a compact and light AUV having the intelligent capabilities. We employed the VARIVEC propeller system utilizing the radio control helicopter elements, which are swash plate and DC servomotors. The VARIVEC propeller can generate six components including thrust, lateral force and moment by changing periodically the blade angle of the propeller during one revolution. It is possible to reduce the number of propellers, mechanism and hence power sources. Our control tests were carried out in an anechoic tank which suppress the reflecting effects of the wall surface. We tested the developed AUV with required performance. Experimental results indicate the effectiveness of our approach. Control of VARIVEC propeller was realized without any difficulty.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.93-102
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• 2000

This paper describes the architecture and characteristics of the satellite modem unit (SMU) developed for the DAMA-SCPC Ground System(DGS), which is a Demand Assignment Multiple Access-Single Channel per Carrier (DAMA-SCPC) satellite network. There are several requirements for the SMU from the system architecture and design concept. To meet these requirements the SMU was designed and implemented by extensively applying digital signal processing (DSP) technique and field programmable gate array (FPGA). The developed SMU met the functional and performance requirements, and has been working well. The measured BER was about 1 $\times$10E-4 in continuous mode(at Eb/No=4.7, FEC=3/4).