• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.2
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• pp.93-99
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• 2011

In this paper, an ATSC(Advanced Television Standard Committee)-M/H(Mobile/Handheld) multiplexer is designed and implemented using an embedded Linux based hardware platform. The ATSC-M/H multiplexer is composed of a CPU(Central Processor Unit), an FPGA(Field-Programmable Gate Array), ASI(Asynchronous Serial Interface)/SMPTE310(Society of Motion Picture and Television Engineers310) interface board, and a GPS(Global Position System) clock processing block. The main functions of the ATSC-M/H multiplexer executed in the CPU and FPGA are described. The operation of the ATSC-M/H multiplexer is verified by processing its broadcast signal on a commercial receiver analyzer.

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.6
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• pp.253-258
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• 2021

In this paper, we developed a hardware and software platform of the real-time data logging system to verify radar FEM (Front-end Module) and signal-processing algorithms. We developed a hardware platform based on FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) and implemented firmware software to verify the various FEMs. Moreover, we designed PC based software platform to control radar logging parameters and save radar data. The developed platform was verified using 24 GHz multiple channel FMCW (Frequency Modulated Continuous Wave) in an environment of stationary and moving targets of chamber room.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1171-1181
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• 2019

Modular Multilevel Converter (MMC)-based HVDC power transmission using a real-time simulator is one of the key technologies in power electronics research. This paper introduces the design methodology of a physical MMC-HVDC control system based on a Field-Programmable Gate Array (FPGA), which has the advantage of high-speed parallel operation, and validates the accuracy of MMC-HVDC control when operated with a Real-Time Digital Simulator (RTDS). Finally, this paper compares and analyzes the characteristics of capacitor voltage balancing methods such as Nearest Level Control (NLC), NLC with a reduced switching frequency, and tolerance band modulation implemented on physical control system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.649-651
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• 2016

본 연구에서는 디지털 신호에 포함되어 있는 잡음을 효과적으로 제거하기 위한 방법으로 프로그램 가능한 디지털 FIR 필터를 제안한다. 이러한 필터는 Altera의 FPGA(Field Programmable Gate Array)인 cyclone II EP2C70F89618를 이용하여 설계하고 구현하였다. 데이터 신호 잡음 제거 알고리즘을 바탕으로 한 영상 신호 제거 결과는 출력 영상으로부터 알 수 있듯이 필터 적용 후 출력 영상은 적용 전의 출력 영상에 비해 월등히 구분이 가능한 출력 영상 특성을 보임을 확인하였다.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.414-415
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• 2019

본 논문은 HVDC(High Voltage Direct Current)에 적용된 MMC(Modular Multilevel Converter)의 제어 알고리즘 개발을 위한 HILS(Hardware In the Loop Simulation)을 위한 모델링 및 HILS 시스템 구축 예를 보인다. 전력 계통, MMC, 풍력 발전 등의 HILS 적용 MATLAB/SIMULINK 모델 및 FPGA(Field Programmable Gate Array)를 이용한 제어기 개발 내용을 보인다. 시뮬레이션 모델과 FPGA 제어기를 이용하여 구축한 OPAL-RT 기반의 실험 결과를 보인다.

• Journal of Information Processing Systems
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• v.15 no.4
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• pp.890-903
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• 2019

The single carrier frequency domain equalization (SC-FDE) technology is an important part of the broadband wireless access communication system, which can effectively combat the frequency selective fading in the wireless channel. In SC-FDE communication system, the accuracy of timing synchronization directly affects the performance of the SC-FDE system. In this paper, on the basis of Schmidl timing synchronization algorithm a timing synchronization algorithm suitable for FPGA (field programmable gate array) implementation is proposed. In the FPGA implementation of the timing synchronization algorithm, the sliding window accumulation, quantization processing and amplitude reduction techniques are adopted to reduce the complexity in the implementation of FPGA. The simulation results show that the algorithm can effectively realize the timing synchronization function under the condition of reducing computational complexity and hardware overhead.

• Annual Conference of KIPS
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• 2013.05a
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• pp.501-503
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• 2013

This project presents a concept of mobile robots using prototypes, computing proposal oriented to embedded systems implementation. We implement our system using GPS module, Ultrasonic sensor(range sensors), H-bridge dual stepper control, DTMF(Dual-tone Multi-Frequency ) and LCD module. In this paper we construct a mechanical simple mobile robot model, which can measure the distance from obstacle with the aid of sensor and should able to control the speed of motor accordingly. Modules were interfaced with FPGA(Field Programmable Gate Array) controller for hardware implementation.

• Journal of Sensor Science and Technology
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• v.31 no.1
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• pp.16-23
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• 2022

Cardiac disease is the most common cause of death worldwide. Therefore, detection and classification of electrocardiogram (ECG) signals are crucial to extend life expectancy. In this study, we aimed to implement an artificial intelligence signal recognition system in field programmable gate array (FPGA), which can recognize patterns of bio-signals such as ECG in edge devices that require batteries. Despite the increment in classification accuracy, deep learning models require exorbitant computational resources and power, which makes the mapping of deep neural networks slow and implementation on wearable devices challenging. To overcome these limitations, spiking neural networks (SNNs) have been applied. SNNs are biologically inspired, event-driven neural networks that compute and transfer information using discrete spikes, which require fewer operations and less complex hardware resources. Thus, they are more energy-efficient compared to other artificial neural networks algorithms.

• Journal of information and communication convergence engineering
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• v.20 no.3
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• pp.212-218
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• 2022

The performance of vision-based intelligent systems, such as self-driving cars and unmanned aerial vehicles, is subject to weather conditions, notably the frequently encountered haze or fog. As a result, studies on haze removal have garnered increasing interest from academia and industry. This paper hereby presents a 4K-capable hardware implementation of an efficient haze removal algorithm with the following two improvements. First, the depth-dependent haze distribution is predicted using a linear model of four haze-relevant features, where the model parameters are obtained through maximum likelihood estimates. Second, the approximated quad-decomposition method is adopted to estimate the atmospheric light. Extensive experimental results then follow to verify the efficacy of the proposed algorithm against well-known benchmark methods. For real-time processing, this paper also presents a pipelined architecture comprised of customized macros, such as split multipliers, parallel dividers, and serial dividers. The implementation results demonstrated that the proposed hardware design can handle DCI 4K videos at 30.8 frames per second.

• Journal of the Korea Institute of Military Science and Technology
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• v.26 no.4
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• pp.324-334
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• 2023

In this paper, the target simulator for RF signals was developed by using VST(Vector Signal Transceiver) and set by real-time signal processing SW programs. A function to process RF signals using FPGA(Field Programmable Gate Array) board was designed. The system functions capable of data processing, raw signals monitoring, target signals(simulated range, velocity) generating and RF environments data analyzing were implemented. And the characteristics of modulated signal were analyzed in RF environment. All function of programs for processing RF signal have options to store signal data and to manage the data. The validity of the signal simulation was confirmed through verification of simulated signal results.