• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.10
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• pp.89-96
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• 2003

In this paper, a CCSDS(Consultative Committee for Space Data Systems) telecommand(TC) decryptor for the security of geostationary communications satellite was implemented. For the confidentiality of CCSDS TC datalink security, Option-A which implements the security services below the transfer sublayer was selected. Also CFB(Cipher Feedback) operation mode of DES(Data Encryption Standard) was used for the encryption of 56-bit data bits in 64-bit codeblock. To verify Decryptor function, the DES CFB logic implemented on A54SX32 FPGA(Field Programmable Gate Array) was integrated with interface and control logics in a PCB(Printed Circuit Board). Using a function test PC, the encrypted codeblocks were generated, transferred into the decryptor, decrypted, and the decrypted codeblocks were transmitted to the function test PC, and then compared with the source codeblocks. Through LED(Light Emitting Diode) ON operation by driving the relay related to Op-code decoded and the comparison between the codeblock output waveforms measured and those simulated, the telecommand decryptor function was verified.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.228-238
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• 2002

This paper presents a digital controller of the electronic ballast using high frequency modulation method for the metal halide lamp. The proposed controller includes the control algorithm for soft starting, no load protection, over current protection and power control. The proposed digital controller, moreover, has the high frequency modulation scheme and the tracking algorithm to avoid acoustic resonance phenomena. For the math production with the low cost using the ASICs (Application Specific Integrated Circuit), the proposed digital controller has been designed with the FPGAs(Field Programmable Gate array) only, without any microprocessor. In this paper, the detail digital control algorithms are described and the experimental results of prototype 150w metal halide electronic ballast are presented.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.97-103
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• 2019

In this paper, we designed and fabricated a receiving modem that can be applied to guided weapons can change real-time targets with little effect of fading. The designed modem consists of synchronous detector, timing error estimator, timing recovery, differential decoder and viterbi decoder, and it's implemented in FPGA so that it can be redesigned and modified according to requirements. The modem board was directly converted from IF frequency to baseband and converted into digital data through ADC. It is confirmed that it is applicable to the guided weapons that changing real-time targets through simulations, measurements and test.

• Nuclear Engineering and Technology
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• v.55 no.4
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• pp.1332-1341
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• 2023

Beam position measurement system can not only provide the beam position monitoring, but also be used for global orbit correction to reduce beam loss risk and maximize acceptance. The Beam Position Monitors (BPM) are installed along the synchrotron to acquire beam position with the front-end electronics and data acquisition system (DAQ). To realize high precision orbit measurement in the main heavy ion synchrotron and cooling storage ring of heavy-ion research facility in Lanzhou (HIRFL-CSRm), a series of alignment and calibration work has been implemented on the BPM and its DAQ system. This paper analyzed the tests performed in the laboratory as well as with beam based on the developed algorithms and hardware. Several filtering algorithms were designed and implemented on the acquired BPM raw data, then the beam position and resolution were calculated and analyzed. The results show that the position precision was significantly improved from more than 100 ㎛ to about 50 ㎛ by implementing the new designed filtering algorithm. According to the analyzation of the measurement results and upcoming physical requirements, further upgrade scheme for the BPM DAQ system of CSRm based on field programmable gate array (FPGA) technology was proposed and discussed.

• Journal of Advanced Navigation Technology
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• v.26 no.6
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• pp.441-447
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• 2022

In this paper, we propose a FLL-assisted-PLL based time synchronization algorithm for telemetry systems where frequency and phase errors exist in time synchronization pulse. The telemetry system may analyze the flight state by acquiring the state information in the distributed system. Therefor, in order to collect each state information without errors, precise time synchronization between the master and the slave is required. At this time, the master's time pulse have frequency and phase changes that can be caused by external and internal factors, so a method to maintain precision time synchronization is essential to provide telemetry data continuously. We propose the FLL-assisted-PLL based algorithm that is capable of high-speed synchronization and has high time synchronization accuracy. The proposed algorithm is verified through python simulation, and the VHDL Logic has been implemented in FPGA to check the performance according to the frequency errors and phase errors.

• Nuclear Engineering and Technology
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• v.56 no.1
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• pp.216-221
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• 2024

Ion cyclotron range of frequency (ICRF) heating system is an important auxiliary heating method in the experimental Advanced Superconducting Tokamak (EAST). In EAST, several megawatts of power are transmitted with coaxial transmission lines and coupled to the plasma. For the long pulse and high power operation of the ICRF waves heating system, it is very important to effectively control the power and initial phase of the ICRF signals. In this paper, a power and phase feedback control system is described based on field programmable gate array (FPGA) devices, which can realize complicated algorithms with the advantages of fast running and high reliability. The transmitted power and antenna phase are measured by a power and phase detector and digitized. The power and phase feedback control algorithms is designed to achieve the target power and antenna phase. The power feedback control system was tested on a dummy load and during plasma experiments. Test results confirm that the feedback control system can precisely control ICRF power and antenna phase and is robust during plasma variations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• Proceedings of the Korean Society of Medical Physics Conference
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• 2002.09a
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• pp.468-470
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• 2002

We have designed X-ray detection system and multi-channel data acquisition system for Spiral CT application. X-ray detection system consists of scintillator and photodiode. Scintillator converts X-ray into visible light. Photodiode converts visible light into electrical signal. The multi-channel data acquisition system consists of analog, digital, master and backplane board. Analog board detects electrical signal and amplifies signal by 140dB. Digital board consists of MUX(Multiplex) which routes multi-channel analog signal to preamplifier, and ADC(Analog to Digital Converter) which converts analog signal into digital signal. Master board supplies the synchronized clock and transmits the digital data to image reconstructor. Backplane provides electrical power, analog output and clock signal. The system converts the projected X-ray signal over the detector array with large gain, samples the data in each channel sequentially, and the sampled data are transmitted to host computer in a given time frame. To meet the timing limitation, this system is very flexible since it is implemented by FPGA(Field Programmable Gate Array). This system must have a high-speed operation with low noise and high SNR(signal to noise ratio), wide dynamic range to get a high resolution image.

• Journal of KIISE
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• v.44 no.9
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• pp.932-945
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• 2017

In this paper, a new hardware and software architecture for a stereo vision processing system including rectification, disparity estimation, and visualization was developed. The developed method, named LArge scale stereo matching method using Support Point Interpolation (LASPI), shows excellence in real-time processing for obtaining dense disparity maps from high quality image regions that contain high density support points. In the real-time processing of high definition (HD) images, LASPI does not degrade the quality level of disparity maps compared to existing stereo-matching methods such as Efficient LArge-scale Stereo matching (ELAS). LASPI has been designed to meet a high frame-rate, accurate distance resolution performance, and a low resource usage even in a limited resource environment. These characteristics enable LASPI to be deployed to safety-critical applications such as an obstacle recognition system and distance detection system for autonomous vehicles. A Field Programmable Gate Array (FPGA) for the LASPI algorithm has been implemented in order to support parallel processing and 4-stage pipelining. From various experiments, it was verified that the developed FPGA system (Xilinx Virtex-7 FPGA, 148.5MHz Clock) is capable of processing 30 HD ($1280{\times}720pixels$) frames per second in real-time while it generates disparity maps that are applicable to real vehicles.

• The Journal of the Acoustical Society of Korea
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• v.23 no.8
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• pp.554-561
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• 2004

As the technologies of semiconductor and multimedia communication have been improved. the high-quality video and the multi-channel audio have been highlighted. MPEG Audio Layer 3 decoder has been implemented as a Processor using a standard. Since the synthesis filter of MPEG-1 Audio Layer 3 decoder requires the most outstanding operation in the entire decoder. the synthesis filter that can reduce the amount of operation is needed for the design of the high-speed processor. Therefore, in this paper, the synthesis filter. the most important part of MPEG Audio, is materialized in FPGA using the method of DAULT (distributed arithemetic look-up table). For the design of high-speed synthesis filter, the DAULT method is used instead of a multiplier and a Pipeline structure is used. The Performance improvement by 30% is obtained by additionally making the result of multiplication of data with cosine function into the table. All hardware design of this Paper are described using VHDL (VHIC Hardware Description Language) Active-HDL 6.1 of ALDEC is used for VHDL simulation and Synplify Pro 7.2V is used for Model-sim and synthesis. The corresponding library is materialized by XC4013E and XC4020EX. XC4052XL of XILINX and XACT M1.4 is used for P&R tool. The materialized processor operates from 20MHz to 70MHz.