• Journal of information and communication convergence engineering
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• v.20 no.3
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• pp.166-173
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• 2022

Recently, studies have been conducted on intelligent transportation systems (ITS) that provide safety and convenience to humans. Systems that compose the ITS adopt architectures that applied the cloud computing which consists of a high-performance general-purpose processor or graphics processing unit. However, an architecture that only used the cloud computing requires a high network bandwidth and consumes much power. Therefore, applying edge computing to ITS is essential for solving these problems. In this paper, we propose an edge artificial intelligence (AI) device based ITS. Edge AI which is applicable to various systems in ITS has been applied to license plate recognition. We implemented edge AI on a field-programmable gate array (FPGA). The accuracy of the edge AI for license plate recognition was 0.94. Finally, we synthesized the edge AI logic with Magnachip/Hynix 180nm CMOS technology and the power consumption measured using the Synopsys's design compiler tool was 482.583mW.

• Nuclear Engineering and Technology
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• v.56 no.1
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• pp.56-63
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• 2024

In high radiation fields, gamma cameras suffer from pulse pile-up, resulting in poor energy resolution, count losses, and image distortion. To overcome this problem, various methods have been introduced to reduce the size of the aperture or pixel, reject the pile-up events, and correct the pile-up events, but these technologies have limitations in terms of mechanical design and real-time processing. The purpose of this study is to develop a real-time gamma camera to evaluate the radioactive contamination in high radiation fields. The gamma camera is composed of a pinhole collimator, NaI(Tl) scintillator, position sensitive photomultiplier (PSPMT), signal processing board, and data acquisition (DAQ). The pulse pile-up is corrected in real-time with a field programmable gate array (FPGA) using the start time correction (STC) method. The STC method corrects the amplitude of the pile-up event by correcting the time at the start point of the pile-up event. The performance of the gamma camera was evaluated using a high dose rate ¹³⁷Cs source. For pulse pile-up ratios (PPRs) of 0.45 and 0.30, the energy resolution improved by 61.5 and 20.3%, respectively. In addition, the image artifacts in the ¹³⁷Cs radioisotope image due to pile-up were reduced.

• Publications of The Korean Astronomical Society
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• v.21 no.2
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• pp.67-74
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• 2006

We have developed a control electronics system for an infrared detector array of KASINICS (KASI Near Infrared Camera System), which is a new ground-based instrument of the Korea Astronomy and Space science Institute (KASI). Equipped with a $512{\times}512$ InSb array (ALADDIN III Quadrant, manufactured by Raytheon) sensitive from 1 to $5{\mu}m$, KASINICS will be used at J, H, Ks, and L-bands. The controller consists of DSP(Digital Signal Processor), Bias, Clock, and Video boards which are installed on a single VME-bus backplane. TMS320C6713DSP, FPGA(Field Programmable Gate Array), and 384-MB SDRAM(Synchronous Dynamic Random Access Memory) are included in the DSP board. DSP board manages entire electronics system, generates digital clock patterns and communicates with a PC using USB 2.0 interface. The clock patterns are downloaded from a PC and stored on the FPGA. UART is used for the communication with peripherals. Video board has 4 channel ADC which converts video signal into 16-bit digital numbers. Two video boards are installed on the controller for ALADDIN array. The Bias board provides 16 dc bias voltages and the Clock board has 15 clock channels. We have also coded a DSP firmware and a test version of control software in C-language. The controller is flexible enough to operate a wide range of IR array and CCD. Operational tests of the controller have been successfully finished using a test ROIC (Read-Out Integrated Circuit).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12A
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• pp.925-932
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• 2009

Precise temperature monitoring is the major preconditioning to supervise quality losses within the transport chain for fresh products. ISO/IEC18000-6REV1 defines new protocols supporting BAP(Battery Assisted Passive) RFID tag which is completely compatible with EPCglobal Class1 Generation2 specification. In this paper, we designed a modem supporting BAP RFID tag with FPGA(Field Programmable Gate Array) and implemented sensor data processing function defined in ISO/IEC18000-6REV1. The transmit block of the modem supports pulse shaping filter and the output signal of the implemented RFID reader is satisfied with the spectrum mask defined in the standard. The receive block of the modem uses Gardner TED to synchronize timing of symbol. In this paper, we designed a modem supporting ISO/IEC18000-6REV1 standard and developed a RFID reader sndard. The developed RFID reader sndard can recognize sensor tag and passive tag in the wireless environment and supports real-time processing of the sensor data in the embedded linux platform.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.11
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• pp.115-120
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• 2005

This paper describes the design and implementation of engineering model(EM) of Mass Memory Unit(MMU) for Science and Technology Satellite 2(STSAT-2) and the results of integration test. The use of Field-Programmable Gate Array(FPGA) instead of using private electric parts makes a miniaturization and lightweight of MMU possible. 2Gbits Synchronous Dynamic Random Access Memory(SDRAM) module for mass memory is used to store payload and satellite status data. Moreover, file system is applied to manage them easily in the ground station. RS(207,187) code improves the tolerance with respect to Single Event Upset(SEU) induced in SDRAM. The simulator is manufactured to verify receiving performance of payload data.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1417-1422
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• 2005

Among the sensors mainly used for displacement measurement, there are a linear CCD(Charge Coupled Device) and a PSD(Position Sensitive Detector) as a non-contact type. Their structures are different very much, which means that the signal processing of both sensors should be applied in the different ways. Most of the displacement measurement systems to get the 3-D shape profile of an object using a linear CCD are a computer-based system. It means that all of algorithms and mathematical operations are performed through a computer program to measure the displacement. However, in this paper, the developed system has microprocessor and other digital components that make the system measure the displacement of an object without a computer. The thing different from the previous system is that AVR microprocessor and FPGA(Field Programmable Gate Array) technology, and a comparator is used to play the role of an A/D(Analog to Digital) converter. Furthermore, an ATC(Automatic Threshold Control) algorithm is applied to find the highest pixel data that has the real displacement information. According to the size of the light circle incident on the surface of the CCD, the threshold value to remove the noise and useless data is changed by the operation of AVR microprocessor. The total system consists of FPGA, AVR microprocessor, and the comparator. The developed system has the improvement and shows the better performance than the system not using the ATC algorithm for displacement measurement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.65-77
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• 2000

We propose a new formulation by quadratic boolean programming to partition circuits for FPGA based reconfigurable circuit boards, in which the routing topology among IC chips are predetermined. The formulation is to minimize the sum of the wire length by considering the nets passing through IC chips for the interconnections between chips which are not adjacent, in addition to the constraints considered by the previous partition methods. We also describe a heuristic method, which consist of module assignment method to efficiently solve the problem. Experimental results show that our method generates the partitions in which the given constraints are all satisfied for all the benchmark circuits tested. The pin utilization are reduced for the most of the circuits and the total wire length of the routed nets are improved up to 34.7% compared to the previous method.

• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.5
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• pp.426-432
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• 2001

This paper is implementation of cellular automata neural network system using evolving hardware concept. This system is a living creatures'brain based on artificial life techniques. Cellular automata neural network system is based on the development and the evolution, in other words, it is modeled on the ontogeny and phylogney of natural living things. The phylogenetic mechanism are fundamentally non-deterministic, with the mutation and recombination rate providing a major source of diversity. Ontogeny is deterministic and local physics. Cellular automata is developed from initial cells, and evaluated in given environment. And genetic algorithms take a part in adaptation process. In this paper we implement this system using evolving hardware concept. Evolving hardware is reconfigurable hardware whose configuration si under the control of an evolutionary algorithm. We design genetic algorithm process for evolutionary algorithm and cells in cellular automata neural network for the construction of reconfigurable system. The effectiveness of the proposed system if verified by applying it to Exclusive-OR.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.10
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• pp.89-96
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• 2003

In this paper, a CCSDS(Consultative Committee for Space Data Systems) telecommand(TC) decryptor for the security of geostationary communications satellite was implemented. For the confidentiality of CCSDS TC datalink security, Option-A which implements the security services below the transfer sublayer was selected. Also CFB(Cipher Feedback) operation mode of DES(Data Encryption Standard) was used for the encryption of 56-bit data bits in 64-bit codeblock. To verify Decryptor function, the DES CFB logic implemented on A54SX32 FPGA(Field Programmable Gate Array) was integrated with interface and control logics in a PCB(Printed Circuit Board). Using a function test PC, the encrypted codeblocks were generated, transferred into the decryptor, decrypted, and the decrypted codeblocks were transmitted to the function test PC, and then compared with the source codeblocks. Through LED(Light Emitting Diode) ON operation by driving the relay related to Op-code decoded and the comparison between the codeblock output waveforms measured and those simulated, the telecommand decryptor function was verified.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.228-238
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• 2002

This paper presents a digital controller of the electronic ballast using high frequency modulation method for the metal halide lamp. The proposed controller includes the control algorithm for soft starting, no load protection, over current protection and power control. The proposed digital controller, moreover, has the high frequency modulation scheme and the tracking algorithm to avoid acoustic resonance phenomena. For the math production with the low cost using the ASICs (Application Specific Integrated Circuit), the proposed digital controller has been designed with the FPGAs(Field Programmable Gate array) only, without any microprocessor. In this paper, the detail digital control algorithms are described and the experimental results of prototype 150w metal halide electronic ballast are presented.