• Advances in Energy Research
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• v.1 no.2
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• pp.97-106
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• 2013

This study designs and tests a photovoltaic system with distributed maximum power point tracking (DMPPT) methodology using a field programmable gate array (FPGA) controller. Each solar panel in the distributed PV system is equipped with a newly designed DC/DC converter and the panel's voltage output is regulated by a FPGA controller using PI control. Power from each solar panel on the system is optimized by another controller where the quadratic maximization MPPT algorithm is used to ensure the panel's output power is always maximized. Experiments are carried out at atmospheric insolation with partial shading conditions using 4 amorphous silicon thin film solar panels of 2 different grades fabricated by Chi-Mei Energy. It is found that distributed MPPT requires only 100ms to find the maximum power point of the system. Compared with the traditional centralized PV (CPV) system, the distributed PV (DPV) system harvests more than 4% of solar energy in atmospheric weather condition, and 22% in average under 19% partial shading of one solar panel in the system. Test results for a 1.84 kW rated system composed by 8 poly-Si PV panels using another DC/DC converter design also confirm that the proposed system can be easily implemented into a larger PV power system. Additionally, the use of NI sbRIO-9642 FPGA-based controller is capable of controlling over 16 sets of PV modules, and a number of controllers can cooperate via the network if needed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1851-1856
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• 2013

An XML is widely used for web services, such as SOAP(Simple Object Access Protocol) and REST (Representational State Transfer), and also de facto standard for representing data. Since the XML parser using DOM(Document Object Model) requires a preprocessing task creating a DOM-tree, and then storing it into memory, embedded systems with limited resources typically employ a streaming XML parser without preprocessing. In this paper, we propose a new architecture for the streaming XML parser using an APSearch(Adaptive Parallel Search) on FPGA(Field Programmable Gate Array). Compared to other approaches, the proposed APSearch parser dramatically reduces overhead on the software side and achieves about 2.55 and 2.96 times improvement in the time needed for an XML parsing. Therefore, our APSearch parser is suitable for systems to speed up XML parsing.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.7
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• pp.949-955
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• 2018

Hardware-in-the-loop (HIL) simulation is a technique that can be employed for developing and testing complex real-time embedded systems. HIL simulation provides an effective platform for verifying power management system (PMS) performance of liquefied natural gas carriers, which are high value-added vessels such as offshore plants. However, HIL tests conducted by research institutes, including domestic shipyards, can be protracted. To address the said issue, this study proposes a field programmable gate array (FPGA) based PMS-HIL simulator that comprises a power supply, consumer, control console, and main switchboard. The proposed HIL simulation platform incorporated actual equipment data while conducting load sharing PMS tests. The proposed system was verified through symmetric, asymmetric, and fixed load sharing tests. The proposed system can thus potentially replace the standard factory acceptance tests. Furthermore, the proposed simulator can be helpful in developing additional systems for vessel automation and autonomous operation, including the development of energy management systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.8
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• pp.1833-1839
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• 2014

In this paper, a systematic demapping algorithm for three-dimensional (3-D) lattice signal constellations is presented. The algorithm consists of decision of an octant, computation of a distance from the origin, and determination of the coordinates of a symbol. Since the algorithm can be extended systematically, it is applicable to the larger lattice constellations. To verify the algorithm, 3-D signal transmission systems with field programmable gate array (FPGA) and $Matlab^{(R)}$ are implemented. And they are exploited to carry out computer simulation. As a result, both hardware and software based systems produce almost the same symbol error rates (SERs) in an additive white Gaussian noise (AWGN) environment. In addition, the hardware based system implemented with an FPGA generates waveforms of 3-D signals and recovers the original binary sequences perfectly. Those results confirm that the algorithm and the implemented 3-D transmission system operate correctly.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.7
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• pp.1289-1295
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• 2007

In this paper, we implemented high-performance concurrent control system which manages whole RF systems with digital type and communicates with remote station on both wire and wireless networking. It consists of FPGA (Field Programmable Gate Array) part which controls forward/reverse LPA (Linear Power Amplifier), forward/reverse LNA (Low Noise Amplifier), channel cut wire/wireless TCP/IP, etc, master microprocessor (AVR), which manages the whole control system, Slave microprocessor which communicates SA (Spectrum Analyzer) and observes frequency spectrum of each channel with the resolution of 5KHz, 10 channel card microprocessor which independently observes each channel card and sets frequency synthesizer in channel cut and other peripherals and logics. The whole system is divided to two parts of H/W (hardware) and S/W (software) considering operational efficiency and concurrency, and implementation and cost. H/W consists of FPGA and microprocessor. We expected the optimized operation through H/W and SW co-design and hybrid H/W architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.8
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• pp.1424-1433
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• 2007

In this paper, we propose a hardware architecture to generate digital hologram using the modified CGH (Computer Generated Hologram) algorithm for hardware implementation and design to FPGA (Field Programmable Gate Array) platform. After analyzing the CGH algorithm, we propose an architecture of CGH cell which efficiently products digital hologram, and design CGH Kernel from configuring CGH Cell. Finally we implement CGH Processor using CGH Kernel, SDRAM Controller, DMA, etc. Performance of the proposed hardware can be proportionally increased through simply addition of CGH Cell in CGH Kernel, since a CGH Cell has operational independency. The proposed hardware was implemented using XC2VP70 FPGA of Xilinx and was stably operated in 200MHz clock frequency. It take 0.205 second for generating $1,280{\times}1,024$ digital hologram from 3 dimensional object which has 40,000 light sources.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.5
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• pp.11-18
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• 2021

The small radio frequency tracking radar is a tracking system with a radio frequency sensor that identifies a target through all-weather radio frequency signal processing for a target and searches, detects and tracks the target for the major target. In this paper, we describe the development of a board equipped with TMS320C6678 and XILINX FPGA (Field Programmable Gate Array), a high-speed multi-core DSP that acquires target information through all-weather radio frequency and identifies a target through real-time signal processing. We propose DSP-FPGA combination architecture for DSP and FPGA selection and signal processing, and also explain the design of SRIO for high-speed data transmission.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.655-658
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• 2016

Xilinx 7-Series FPGA(Field Programmable Gate Array)s mainly used for the implementation of high-performance digital circuit have SRAM-type configuration memory and can malfunction when soft errors occur in their configuration memory. SEM(Soft Error Mitigation Controller) offered by Xilinx helps users mitigate the influence of soft errors in configuration memory. When soft errors occur, SEM Controller can recover the state of FPGA through partial reconfiguration if the soft errors are correctable by ECC(Error Correction Code) and CRC(Cyclic Redundancy Code). This paper presents the availability analysis of Xilinx 7-Series FPGAs against soft errors under the protection of the SEM Controller. Availability functions are derived and compared according to the correction capability of the SEM Controller. The result may help to estimate the reliability of SRAM-based FPGA running in an environment where soft errors may occur.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.1
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• pp.9-14
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• 2019

A small millimeter-wave tracking radar is a pulse-based radar that searches, detects, and tracks a target in real time through a TWS (Track While Scan) method for a traps target on the sea with a large RCS running at low speed. It is necessary to develop a board equipped with a high-speed CPU to acquire and track target information through LPRF, DBS, and HRR signal processing techniques for a trap target operating various kinds of dexterous objects such as chaff and decoy, We designed a signal processor structure including DFT (Discrete Fourier Transform) module design that can perform real - time FFT operation using FPGA (Field Programmable Gate Array) and verified the signal processor implemented through performance test.

• Journal of IKEEE
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• v.27 no.3
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• pp.273-279
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• 2023

The use of line memory is essential for image filtering in image processing hardware. After input data is stored in line memory, filtering is performed after synchronization to use the stored data. A sync generator is used for synchronization, and in the case of a conventional sync generator, the input sync signal is delayed by one row of the input image. If a signal delayed by two rows is required, it is necessary to connect two modules. This approach increases the size of the hardware and cannot be designed efficiently. In this paper, we propose a sync generator that generates multiple types of delayed signals by adding a finite state machine. The hardware design was coded in Verilog HDL, and performance is verified by applying it to image processing hardware using field programmable gate array board.