• 디지털산업정보학회논문지
• /
• 제18권1호
• /
• pp.1-9
• /
• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• ETRI Journal
• /
• 제35권3호
• /
• pp.523-529
• /
• 2013

Subquadratic space complexity multipliers for optimal normal bases (ONBs) have been proposed for practical applications. However, for the Gaussian normal basis (GNB) of type t > 2 as well as the normal basis (NB), there is no known subquadratic space complexity multiplier. In this paper, we propose the first subquadratic space complexity multipliers for the type 4 GNB. The idea is based on the fact that the finite field GF($2^n$) with the type 4 GNB can be embedded into fields with an ONB.

• 한국통신학회논문지
• /
• 제36권4C호
• /
• pp.217-225
• /
• 2011

본 논문에서는 영상의 지역 특성별로 보간 방법을 적응적으로 선택하여 적용하는 효과적인 디인터레이싱 알고리듬을 제안한다. 기존의 알고리듬들의 경우 각기 다른 방법으로 방향성을 구하기 때문에 영상의 지역 특성별로 성능이 다르게 나오는 경우가 있다. 또한, FDD(Fine Directional De-interlacing) 알고리듬의 경우 PSNR(Peak Signal-to-Noise Ratio)은 다른 알고리듬들에 비해 높게 나오지만 계산량이 많다는 단점이 있다. 이를 보안하기 위해 본 논문에서는 여러 영상들에서 계산량은 적으면서 화질 성능은 뛰어난 LA(Line Average), MELA(Modified Edge-based Line Average), LCID(Low-Complexity Interpolation Method for De-interlacing) 알고리듬들 중 지역복잡도 (DoLC, Degree of Local Complexity)별로 효과적인 알고리듬을 학습하여 이를 이용하여 보간을 수행하는 디인터레이싱 방법을 제안한다. 실험 결과 제안하는 방법은 좋은 성능에 비해 계산량이 적은 LCID 알고리듬과 비슷한 계산량을 보이면서 객관적 화질이 우수한 FDD, MELA 알고리듬보다 PSNR로 대표되는 객관적 화질과 주관적 화질 측면에서 우수한 결과를 나타내는 것을 알 수 있다.

• 대한임베디드공학회논문지
• /
• 제11권4호
• /
• pp.227-233
• /
• 2016

Efficient finite field arithmetic is essential for fast implementation of error correcting codes and cryptographic applications. Among the arithmetic operations over finite fields, the multiplication is one of the basic arithmetic operations. Therefore an efficient design of a finite field multiplier is required. In this paper, two new bit-parallel systolic multipliers for $GF(2^m)$ fields defined by AOP(all-one polynomial) have proposed. The proposed multipliers have a little bit greater space complexity but save at least 22% area complexity and 13% area-time (AT) complexity as compared to the existing multipliers using AOP. As compared to related works, we have shown that our multipliers have lower area-time complexity, cell delay, and latency. So, we expect that our multipliers are well suited to VLSI implementation.

• 디지털산업정보학회논문지
• /
• 제16권2호
• /
• pp.1-9
• /
• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• 한국콘텐츠학회논문지
• /
• 제18권11호
• /
• pp.484-492
• /
• 2018

본 연구의 목적은 수화물 검사 과제에서 장 복잡성과 위험물품 종류가 탐지율과 반응시간에 미치는 효과를 검증하는 것이었다. 참가자는 C 대학 학부생 62명이었고(남 45.2%, 여 54.8%), 평균 나이는 22.88세였다. 가상 수화물 심사(신호 탐지) 과제를 개발하여 사용하였고 참가자들은 실험에 대한 오리엔테이션과 과제 연습에 참가한 후 본 실험에 참가하였다. 참가자들은 총 200개의 수화물 검사 과제를 실시하였고 40개(20%)가 위험 물품을 포함하고 있었다. 본 연구의 독립변인 중 장 복잡성은 상(20개), 중(14개), 하(8개) 세 수준으로 위험 물품의 종류는 총, 칼, 액체, 그리고 라이터 4가지로 설정하였다. 종속변인은 위험 물품이 있는 이미지 중 표적 신호를 탐지한 비율(%)이었다. 연구 결과 장이 복잡할수록 탐지율이 유의미하게 감소하였고, 반응시간은 증가하였다. 그리고 위험 물품의 종류에 따라 탐지율과 반응시간은 달라지는 것으로 나타났다. 특히 칼의 탐지율이 가장 높았고 반응시간은 가장 짧았으며 액체의 탐지율이 가장 낮고, 반응시간은 길었다. 장 복잡성과 위험 물품의 상호작용 효과 역시 탐지율과 반응시간에 영향을 미쳤다. 칼은 장 복잡성에 영향을 받지 않았고, 라이터와 같이 작은 물품이 장 복잡성의 영향을 가장 크게 받은 것으로 나타났다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권1호
• /
• pp.118-125
• /
• 2016

This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.

• 한국통신학회논문지
• /
• 제25권3B호
• /
• pp.510-518
• /
• 2000

A new video interpolation technique based on variable skip rate of video sequence is proposed in this paper. in the proposed technique. the determination whether a frame is skipped or not is done by the degree of motion complexity of the frame. If the motion complexity of a frame is low the frame is skipped. otherwise it is coded and transmitted. To determine the motion complexity of a frame a new technique using MEF (moving edge in frame),the set of pixels considered as moving edges in a frame. is introduced. In the course of decoding and interpolating of receiver., the motion field is segmented. For the purpose of dividing vector field morphological filtering is applied. Morphological filtering also used to smooth the boundaries between the changed and unchanged region. In the simulation results, the proposed technique shows higher quality and lower fluctuation of picture quality than the conventional techniques on conditioning of the same bit rate.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제6권9호
• /
• pp.2351-2369
• /
• 2012

This paper describes interpolation method of motion field in the Wyner-Ziv video coding (WZVC) based on Expectation-Maximization (EM) algorithm. In the EM algorithm, the estimated motion field distribution is calculated on a block-by-block basis. Each pixel in the block shares similar probability distribution, producing an undesired blocking artefact on the pixel-based motion field. The proposed interpolation techniques are Bicubic and Lanczos which successively use 16 and 32 neighborhood probability distributions of block-based motion field for one pixel in k-by-k block on pixel-based motion field. EM-based WZVC codec updates the estimated probability distribution on block-based motion field, and interpolates it to pixel resolution. This is required to generate higher-quality soft side information (SI) such that the decoding algorithm is able to make syndrome estimation more quickly. Our experiments showed that the proposed interpolation methods have the capability to reduce EM-based WZVC decoding complexity with small increment of bit rate.

• ETRI Journal
• /
• 제39권4호
• /
• pp.570-581
• /
• 2017

Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit-parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application-specific integrated circuit and field-programmable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.