• Journal of Electrical Engineering and Technology
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• v.12 no.6
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• pp.2227-2236
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• 2017

In order to solve the neutral-point voltage fluctuation problem of three-phase three-level T-type inverters (TPTLTIs), the unbalance characteristics of capacitor voltages under different switching states and the mechanism of neutral-point voltage fluctuation are revealed. Based on the mathematical model of a TPTLTI, a feed-forward voltage balancing control strategy of DC-link capacitor voltages error is proposed. The strategy generates a DC bias voltage using a capacitor voltage loop with a proportional integral (PI) controller. The proposed strategy can suppress the neutral-point voltage fluctuation effectively and improve the quality of output currents. The correctness of the theoretical analysis is verified through simulations. An experimental prototype of a TPTLTI based on Digital Signal Processor (DSP) is built. The feasibility and effectiveness of the proposed strategy is verified through experiment. The results from simulations and experiment match very well.

• Journal of Power Electronics
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• v.13 no.3
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• pp.400-408
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• 2013

This paper presents a discrete state-space controller using state feedback control and feed-forward decoupling to provide a desirable control bandwidth and control stability for dynamic voltage restorers (DVR). The paper initially discusses three typical applications of a DVR. The load-side capacitor DVR topology is preferred because of its better filtering capability. The proposed DVR controller offers almost full controllability because of the multi-feedback of state variables, including one-beat delay feedback. Feed-forward decoupling is usually employed to prevent disturbances of the load current and source voltage. Directly obtaining the feed-forward paths of the load current and source voltage in the discrete domain is a complicated process. Fortunately, the full feed-forward decoupling strategy can be easily applied to the discrete state-space controller by means of continuous transformation. Simulation and experimental results from a digital signal processor-based system are included to support theoretical analysis.

• Journal of Power Electronics
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• v.14 no.5
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• pp.1047-1056
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• 2014

In most grid-connected inverters (GCI) with an LCL filter, since the design of both the LCL filter and the controller is done separately, considerable tuning efforts have to be exerted when compared to inverters using an L filter. Consequently, an integrated co-design of the filter and the controller for an LCL-type GCI is proposed in this paper. The control strategy includes only a PI current controller and a proportional grid voltage feed-forward controller. The capacitor is removed from the LCL filer and the design procedure starts from an L-type GCI with a PI current controller. After the PI controller has been settled, the capacitor is added back to the filter. Hence, it introduces a resonance frequency, which is identified based on the crossover frequencies to accommodate the preset PI controller. Using the proposed co-design method, harmonic standards are satisfied and other practical constraints are met. Furthermore, the grid voltage feed-forward control can bring an inherent damping characteristic. In such a way, the good control performance offered by the original L-type GCI and the sharp harmonic attenuation offered by the latter designed LCL filter can be well integrated. Moreover, only the grid current and grid voltage are sensed. Simulation and experimental results verify the feasibility of the proposed design methodology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.276-281
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• 2010

A 2.5 V feed-forward second-order deltasigma modulator for audio application is presented. A 9-level quantizer with a tree-structured dynamic element matching (DEM) was employed to improve the linearity by shaping the distortion resulted from the capacitor mismatch of the feedback digital-toanalog converter (DAC). A chopper stabilization technique (CHS) is used to reduce the flicker noise in the first integrator. The prototype delta-sigma analogto-digital converter (ADC) implemented in a 65 nm 1P8M CMOS process occupies 0.747 $mm^2$ and achieves 109.1 dB dynamic range (DR), 85.4 dB signal-to-noise ratio (SNR) in a 24 kHz audio signal bandwidth, while consuming 14.75 mW from a 2.5 V supply.

• Journal of Power Electronics
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• v.17 no.4
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• pp.1037-1047
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• 2017

The Differential Power Processing (DPP) converter is a promising multi-module photovoltaic inverter architecture recently proposed for photovoltaic systems. In this paper, a DPP converter architecture, in which each PV-panel has its own DPP converter in shunt, performs distributed maximum power point tracking (DMPPT) control. It maintains a high energy conversion efficiency, even under partial shading conditions. The system architecture only deals with the power differences among the PV panels, which reduces the power capacity of the converters. Therefore, the DPP systems can easily overcome the conventional disadvantages of PCS such as centralized, string, and module integrated converter (MIC) topologies. Among the various types of the DPP systems, the feed-forward method has been selected for both its voltage balancing and power transfer to a modified H-bridge inverter that needs charge balancing of the input capacitors. The modified H-bridge multi-level inverter had some advantages such as a low part count and cost competitiveness when compared to conventional multi-level inverters. Therefore, it is frequently used in photovoltaic (PV) power conditioning system (PCS). However, its simplified switching network draws input current asymmetrically. Therefore, input capacitors in series suffer from a problem due to a charge imbalance. This paper validates the operating principle and feasibility of the proposed topology through the simulation and experimental results. They show that the input-capacitor voltages maintain the voltage balance with the PV MPPT control operating with a 140-W hardware prototype.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.57-63
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• 2014

This paper proposes an architecture of $3^{rd}$ order SDM(Sigma-Delta Modulator) with delayed feed-forward path in order to reduce the power consumption and area. The proposed SDM improve the architecture of conventional $3^{rd}$ order SDM which consists of two integrators. The proposed architecture can increase the coefficient values of first stage doubly by inserting the delayed feed-forward path. Accordingly, compared with the conventional architecture, the capacitor value($C_I$) of first integrator is reduced by half. Thus, because the load capacitance of first integrator became the half of original value, the output current of first op-amp is reduced as 51% and the capacitance area of first integrator is reduced as 48%. Therefore, the proposed method can optimize the power and the area. The proposed architecture in this paper is simulated under conditions which are supply voltage of 1.8V, input signal 1Vpp/1KHz, signal bandwidth of 24KHz and sampling frequency of 2.8224MHz in the 0.18um CMOS process. The simulation results are SNR(Signal to Noise Ratio) of 88.9dB and ENOB(Effective Number of Bits) of 14-bits. The total power consumption of the proposed SDM is $180{\mu}W$.

• Journal of IKEEE
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• v.20 no.3
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• pp.318-321
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• 2016

As IoT industry are growing fast, The importance of power management system is also being magnified. CMOS High power-supply rejection ratio(PSRR) Low-dropout(LDO) regulator is achieved by the proposed ripple Subtractor, Feed-forward capacitor and OTA in this paper. The LDO is implemented in $0.18-{\mu}m$ CMOS technology. With the proposed structures, in the maximum loading of 40mA, Simulation result achieves PSRR of -73.4dB at 500kHz and PSRR better than -40dB when frequency is below 10MHz with $6.8-{\mu}F$ output capacitor.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.627-628
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• 2006

A low-voltage switched-capacitor $2^{nd}$-order $\Sigma\Delta$ modulator using full feed-forward is introduced. It has two advantages: the unity signal transfer function and reduced signal swings inside the $\Sigma\Delta$ loop. These features greatly relax the DC gain and output swing requirements for Op-Amp in the low-voltage $\Sigma\Delta$ modulator. Implemented by a 0.18-${\mu}m$ CMOS technology, the $\Sigma\Delta$ modulator satisfies performance requirements for WCDMA and CDMA2000 standards.

• Journal of Power Electronics
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• v.13 no.6
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• pp.991-999
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• 2013

In this paper, a fast transient buck converter using hysteresis PWM control is presented. The proposed control method is based on hysteresis control of the capacitor C voltage. This offers a faster transient response to meet the challenges of the power supply requirements for fast dynamic input and load changes. It also provides better stability and solves the compensation problem of the error amplifier in conversional voltage PWM control. Finally, the steady-state and dynamic operation of the proposed control method are analyzed and verified by simulation and experimental results.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.193-194
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• 2012

동일한 패시브 소자를 사용한 조건에서 부하 변동에 대한 출력 전압 레귤레이션을 향상시키기 위해서 출력 전류의 피드포워드 기법이 많이 이용되고 있다. 그러나 이러한 방법은 출력 전류를 센싱하기 위해 직렬 저항 사용이나 홀센서와 같은 전류 센서를 사용하게 되는데 이는 각각 저항 손실 증가와 가격 증가로 이어지게 되는 단점이 있다. 이에 이러한 출력 전류 센서 없이 출력 캐패시터의 전압을 이용하여 출력 전류를 간접적으로 센싱하여 출력 전류 피드포워드를 하는 기법을 제안하고 이를 시뮬레이션을 통해 검증한다.