• Progress in Superconductivity and Cryogenics
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• v.1 no.1
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• pp.28-32
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• 1999

We have performed an EMTDC simulation for the current limiting effects of a superconducting fault current limiter (SFCL). The fault currents in the 154 kV transmission line between the arbitrary S1 and S2 substations increased up to 54 KA and 60 KA during the line-to-line and three phase faults, respectively. The SFCL with 100$\omega$ of resistance after quench limited the currents to less than 17 KA within a half cycle. This limited current is well below the upper limit of a circuit breaker, suggesting that the resistance of the SFCL in the transmission line is sufficient.

• Proceedings of the KIEE Conference
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• summer
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• pp.619-621
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• 2004

This paper presents the rapid and accurate algorithm for fault discrimination in transmission lines. When faults occur in transmission lines, fault discrimination is very important. If high impedance faults occur in transmission lines, it cannot be detected by overcurrent relays. The method using current and voltage cannot discriminate high impedance fault. Because of this reason this paper uses voltage and zero sequence current, and the proposed algorithm uses fuzzy logic method. This algorithm uses voltage and zero sequence current per period in case of faults. Single line ground fault and three-phase fault can be detective using voltage. Two-line ground fault and line to line fault and high impedance can be detected using zero sequence current. To prove the performance of the algorithm, it test algorithm with signal obtained from ATPDraw simulation.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1972-1975
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• 2002

A new test approach based on a supply current test method is proposed for testing open faults in bipolar logic circuits. In the approach, only the open faults are detected by the supply current test method, which are difficult to be detected by functional test methods. The effectiveness of the approach is examined experimentally on open fault detection in TTL combinational circuits. The results shows that higher fault coverage can be established by applying a small number of test input vectors of the supply current test method after test vectors of functional test methods based on stuck-at models.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.51 no.5
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• pp.209-216
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• 2002

Recently, there is greater demand for stable supply of electric power as higher level of our living. It becomes the important problem that the cause of fault in power system is found out in early stage, if once it occurs. In this respect, accurate classification of arcing faults in power systems is vitally important. This paper presents a new classification method for arcing faults in power system. To obtain data of various faults including high impedance fault(HIF) and low impedance fault(LIF), HIF model with the ZnO arrester is adopted and implemented within the overall transmission system model based on the electromagnetic transients program(EMTP). Results of phase plane trajectory if Clarke modal transformation using postfault current and voltage are utilized to classify types of arcing faults. The performance of the proposed method is tested on a typical 154 kV korean transmission system under various fault conditions. As can be seen from results, phase plane trajectory of postfault current should be combined with that of o component from Clarke modal transformation to give reliability of clear fault classification. Thus the proposed method can classify arcing faults including LIFs and HIFs accurately in power systems.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.8
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• pp.1460-1466
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• 2011

This paper proposes the algorithm for discriminating faults from the variation due to the operation of non-linear components to prevent the mal-operation of protection relay in the distribution system. An IEEE 13 node test feeder is modeled to analyze the characteristics of the fault and each variation using EMTP-RV. Simulations with various operating conditions of transformers, non-linear loads, and unbalanced loads are performed using the test feeder model. Based on simulation results, the wavelet transform is adopted to analyze the current waveforms from the faults and variations to find out the differences between them and the algorithm for discriminating faults from the variation is proposed. The proposed algorithm is verified by using the current waveforms simulated in the KEPCO's distiribution system and IEEE 13 node test feeder.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.635-637
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• 2001

The faults of the squirrel cage induction motor is grew increasingly complex as the faults resulting in the shorting of a stator winding and the broken rotor bar or cracked rotor end ring, bearing faults, and so on. The users of electrical machines initially relied on simple protections such as over-current, over-voltage, earth-fault, etc. to ensure safe and reliable operation. but this method cause heavy financial losses and the threat of safety therefore it has now become very important to diagnose faults at there very inception. in this paper, we are going to discuss the detection method of broken rotor bar of squirrel cage induction motor by the motor current signal analysis(MCSA) and the opening terminal voltage signal analysis.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.173-184
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• 1994

BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.243-245
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• 2001

This paper presents a new classification method for high impedance faults in power systems. Results of phase plane trajectory with Clarke modal transformation using postfault current and voltage are utilized to classify types of arcing faults. The performance of the proposed method is tested on a typical 154 kV korean transmission system under various fault conditions using EMTP. As can be seen from results, phase plane trajectory of postfault current should be combined with that of o component from Clarke modal transformation to give reliability of clear fault classification. Thus the proposed method can classify arcing faults including LIFs and HIFs accurately in power systems.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.49 no.8
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• pp.405-411
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• 2000

When faults occur in transmission lines, the classification of faults is very important. If the fault is HIF(High Impedance Fault), it cannot be detected or removed by conventional overcurrent relays (OCRs), and results in fire hazards and causes damages in electrical equipment or personal threat. The fast discrimination of fault needs to effective protection and treatment and is important problem for power system protection. This paper propolsed the fault detection and discrimination algorithm for LIFs(Low Impedance Faults) and HIFs(High Impedance Faults). This algorithm uses artificial neural networks and variation of 3-phase maximum currents per period while faults. A double lines-to-ground and line-to-line faults can be detected using Neural Network. Also, the other faults can be detected using the value of variation of maximum current. Test results show that the proposed algorithms discriminate LIFs and HIFs accurately within a half cycle.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.1
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• pp.1-11
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• 1997

A BiCMOS circuit consists of the CMOS part which performs the logic function, and the bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential beavior. Also, stuck-on faults enhanced IDDQ (quiscent power supply current) at steady state. In this paper, a method is proposed which efficiently generates test patterns to detect stuck-open faults and stuck-on faults in BiCMOS circuits. The proposed method divides the BiCMOS circuit into pull-up part and pull-down part, and generates test patterns detect faults occured in each part by structural property of the BiCMOS circuit.