• Journal of Internet Computing and Services
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• v.16 no.5
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• pp.75-86
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• 2015

Internet of Thing (IoT) computing is an environment where various devices with sensors and actuators are connect, and interact together to acquire contexts and provide useful services. With the advances of IoT technologies, its usability becomes an in important issue. However, there exist various types of faults in IoT computing which are not conventionally addressed in software research community. Providing reliable IoT services is challenging. In this paper, we present a hierarchy of IoT faults and analyze causes and symptoms of the faults. Based on the analysis, we define effective methods for managing IoT faults. We believe that our proposed framework for managing IoT faults can be utilized in reducing the development cost of IoT applications and enhancing the quality of the applications.

• Economic and Environmental Geology
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• v.15 no.2
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• pp.65-88
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• 1982

In the last ten years, marine geological and geophysical survey and research were conducted by Japanese, Russian and American scientists in the East Sea of Korea (Japan Sea). Many research results were published. However, regional research of the geology of the continental margin of the Korean Peninsula was not conducted. This study has made on attempt to classify submarine strata and stratigraphic boundaries. The study has revealed characters of submarine geology and structure. Isopach maps of each identified stratigraphic unit have been constructed as the results of this study. The study was conducted on the basis of analyses of marine seismic surveys carried out in the continental margin of the East Sea between Kangneung and Pohang. Three depositional basins were identified in the study area and they were named as, Mukho Basin, Hupo Basin and Pohang Basin. The Mukho Basin is developed in continental slope and shelf in the area between Kangneung and Samcheog. Quaternary and Pliocene sediments attain a maximum thickness of 900 m. Basement rocks are interpreted as granite and gneiss. They are correlated with granite-gneiss of the Taebaecksan Series of Pre-cambrian age and the Daebo granite of Jurassic age. The Hupo Basin is developed in the continental shelf between Uljin and Youngdeok. Quaternary and Pliocene sediments attain a maximum thickness of 600 m. Basement rocks were interpreted as granite and gneiss and they are correlated with metamorphic rocks of Pre-cambrian age and the Daebo granites, comprising the Ryongnam Massif. The Pohang Basin is developed in the area between Pohang and Gangu. This basin contains Miocene and older sediments. Basement rocks are not shown. Many faults are developed within the continental shelf and slope. These faults strike parallel with the coast line. A north-south direction is predominant in the southern study area. However, in the northern study area the faults strike north, and north-west. The faults are parallel to each other and are step faults down-thrown to the east or west, forming horst and graben structures which develop into sedimentary basins. Such faults caused the development of submarine banks along the boundary between the continental shelf and slope. This bank has acted as a barrier for deposition in the Hupo Basin. Paleozoic sedimentary rocks distributed widely in the adjacent land area are absent in the Mukho Basin. This suggests that the area of the basin was situated above the sea level until the Pliocene time. The study area contains Pliocene sediments in general. These sediments overlie the basement complex composed of metamorphic rocks, granites, Cretaceous (Kyongsang System) sedimentary rocks and Miocene sedimentary rocks. These facts lead to a conclusion that the continental shelf and slope of the study area were developed as a result of displacements along faults oriented parallel to the present coast line in the post Miocene time.

• The Journal of Engineering Geology
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• v.26 no.3
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• pp.393-401
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• 2016

In the present study, fault attitudes and the locations of appearance of faults in tunnel faces were predicted by analyzing the trajectory of the maximum longitudinal displacement immediately before the appearance of faults through three-dimensional finite element analysis. A total of 28 fault attitude models were used in the analysis. Those faults that have drives with dip appear first in the upper part of tunnel faces as tunnel excavation progresses and their maximum longitudinal displacement shows a tendency to move from the middle part to the upper part of tunnel faces. Those faults that have drives against dip appear first in the lower part of tunnel faces as tunnel excavation progresses and their maximum longitudinal displacement shows a tendency to move from the middle part or middle upper part to the lower part of tunnel faces. In addition, when the dip of faults is larger the maximum longitudinal displacement moves from the left upper part toward the wall part in the case of drive with dip models and from the left lower part toward the wall part in the case of drives against dip models. Therefore, it was indicated that the attitudes of faults distributed ahead of tunnel faces and the locations where faults appear in tunnel faces can be predicted by analyzing the longitudinal displacement trajectory of tunnel faces following excavation.

• International Journal of Control, Automation, and Systems
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• v.4 no.6
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• pp.763-768
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• 2006

The two-for-one(TFO) twister is precision machinery that twists fibers rapidly under constant tension. Since the quality of the twisted yarn is directly deteriorated by faults of the twister, such as the distortion of the spinning axis, bearing abrasion, and tension irregularity, it is important to detect faults of the TFO twister at an early stage. In this research, a new algorithm is proposed to detect faults of the TFO twister and their causes, by measuring the vibrations of the TFO twister and obtaining frequency components with a FFT algorithm. The TFO twister with faults showed increased vibrations and each fault generated vibrations at different frequencies. By analyzing changes of characteristics of vibrations, we can determine faulty twisters. The proposed fault detection algorithm can be implemented cheaply with a signal processor chip. It can be used to find when to repair a faulty TFO twister without much loss of yam on-line.

• The Transactions of the Korea Information Processing Society
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• v.5 no.11
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• pp.2989-2996
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• 1998

As the circuit density of VLSI grows and its performance improves, delay fault testing of VLSI becomes very important. Delay faults in a circuit can be categorized into two classes, gate delay faults and path delay faults. This paper proposed two methods in dynamic memory usage in the path delay fault simulation. The first method is similar to that used in concurrent fault simulation for stuck-at faults and the second method reduces dynamic memory usage by not inserting a fault descriptor into the fault list when its value is X. The second method, called Implicit-X method, showed superior performance in both dynamic memory usage and simulation time than the first method, called Concurrent-Simulation-Like method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.100-105
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• 2003

In this paper, we propose the novel test method effectively to detect short and open faults in CMOS op-amp. The proposed method uses a sinusoidal signal with higher frequency than unit gain bandwidth. Since the proposed test method doesn't need complex algorithm to generate test pattern, the time of test pattern generation is short, and test cost is reduced because a single test pattern is able to detect all target faults. To verify the proposed method, CMOS two-stage operational amplifier with short and open faults is designed and the simulation results of HSPICE for the circuit have shown that the proposed test method can detect short and open faults in CMOS op-amp.

• Journal of Sensor Science and Technology
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• v.22 no.1
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• pp.28-37
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• 2013

This paper presents a fault-tolerant control technique for wind turbine systems with sensor and actuator faults. The control objective is to maximize power production and minimize turbine loads by calculating a desired pitch angle within their limits. Any fault with a sensor and actuator can cause significant error in the pitch position of the corresponding blade. This problem may result in insufficient torque such that the power reference cannot be achieved. In this paper, a fault-tolerant control technique using a robust dynamic inversion observer and control allocation is employed to achieve successful pitch control despite these faults in the sensor and actuator. The observer based detection method is used to detect and isolate sensor faults by checking whether errors are larger than threshold values. In addition, the control allocation technique is adopted to tolerate actuator fault. Control allocation is one of the most commonly used fault-tolerant control techniques, especially for over-actuated systems. Further, the control allocation method can be used to achieve the power reference even in the event of blade actuator fault by redistributing the lost torque due to erroneous pitch position into non-faulty blade actuators. The effectiveness of the proposed method is demonstrated through simulations with a benchmark model of the wind turbine.

• Journal of international Conference on Electrical Machines and Systems
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• v.3 no.2
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• pp.190-199
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• 2014

In the last years, fault problem in power electronics has been more and more investigated both from theoretical and practical point of view. The fault problem can cause equipment failure, data and economical losses. And the analyze system require to ensure fault problem and also rectify failures. The current errors on these faults are applied for identified type of faults. This paper presents technique to detection and identification faults in three-phase voltage source inverter (VSI) by using time-frequency distribution (TFD). TFD capable represent time frequency representation (TFR) in temporal and spectral information. Based on TFR, signal parameters are calculated such as instantaneous average current, instantaneous root mean square current, instantaneous fundamental root mean square current and, instantaneous total current waveform distortion. From on results, the detection of VSI faults could be determined based on characteristic of parameter estimation. And also concluded that the fault detection is capable of identifying the type of inverter fault and can reduce cost maintenance.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.10
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• pp.983-990
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• 2008

This paper presents the fault detection and diagnosis(FDD) algorithm to enhance reliability of a longitudinal controller for an autonomous All-Terrain Vehicle(ATV). The FDD is designed to monitor and identify faults which may occur in distributed hardware used for longitudinal control, e.g., DSPs, CAN, sensors, and actuators. The proposed FDD is an integrated approach of decentralized and centralized FDD. While the former is processed in a DSP and suitable to detect faults in a single hardware, it is sensitive to noise and disturbance. On the other hand, the latter is performed via communication and it detects and diagnoses faults through analyzing concurrent performances of multiple hardware modules, but it is limited to isolate faults specifically in terms of components in the single hardware. To compensate for disadvantages of each FDD approach, two layered structure including both decentralized and centralized FDD is proposed and it allows us to make more robust fault detection and more specific fault isolation. The effectiveness of the proposed method will be validated experimentally.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.22-34
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• 1999

In this paper, an efficient test algorithm for embedded dual-port memories is presented. The proposed test algorithm can be used to test embedded dual-port memories faster than the conventional multi-port test algorithms and can be used to completely detect stuck-at faults, transition faults and coupling faults which are major target faults in embedded memories. Also, in this work, BIST which performs the proposed memory testing algorithm is designed using Verilog-HDL, and simulation and synthesis for BIST are performed using Cadence Verilog-XL and Synopsys Design-Analyzer. It has been shown that the proposed test algorithm has high efficiency through experiments on various size of embedded memories.