• Journal of The Geomorphological Association of Korea
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• v.28 no.3
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• pp.63-83
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• 2021

In the southeastern part of the Korean Peninsula, the Yangsan Fault, an active fault zone, has developed. Many earthquakes occur around these faults, and the possibility of earthquakes occurring along the branch faults is being discussed. On the other hand, the Yeongdeok Fault is reported in Yeongdeok-gun, which is the northern part of the Yangsan fault. In this study, goemorphic characteristics of a set faults found on the outcrop of the gentle slope of the coast of Byeonggok-myeon were analyzed and granulometric and geochemical characteristics of sediments and other materials, including fault gouges were analyzed. The outcrop of Byeonggok-myeon is the part of the fault core and can be divided into two parts. Theses fault are formed on the upper part of the Mesozoic bedrock and the tertiary sedimentary layer of red sand-supported clasts are covered in several sedimentary units. The faults were normal fault sets, and a number of vertical cracks were developed, and glossy surfaces were observed in the fault area. It appears that these faults have occurred after alluvial deposition had been formed. In the case of samples from fault gouges, there were differences in particle size and geochemical characteristics from the surrounding area.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.6
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• pp.614-619
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• 2023

The fault current limiting characteristics of three-phase transformer type superconducting fault current limiter (SFCL), which consisted of three-phase primary and secondary windings wound on E-I iron core, one high-TC superconducting (HTSC) element connected with the secondary winding of one phase and another HTSC element connected in parallel with other two secondary windings of two phases, were analyzed. Unlike other three-phase transformer type SFCLs with three HTSC elements, three-phase transformer type SFCL using double quench has the merit to perform fault current limiting operation for three-phase ground faults with two HTSC elements. To verify its proper three-phase ground fault current limiting operation, three-phase ground faults such as single-line ground, double-line ground and triple-line ground faults were generated in three-phase simulated power system installed with three-phase transformer type SFCL using double quench. From analysis of its fault current limiting characteristics based on tested results, three-phase transformer type SFCL using double quench was shown to be effectively operated for all three-phase ground faults.

• Proceedings of the KIEE Conference
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• 2007.11b
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• pp.37-39
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• 2007

In the faults of power line, single line ground and line-to-line fault make power system to unbalanced. These fault currents make unbalanced power system. This paper suggests the simulation results of dynamic characteristic of HTS cable system under unbalanced faults condition using EMTDC, Quench phenomenon and current limiting effects are observed. However, quench on the HTS is destroy cable system, coordination with SFCL has to be considered.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.807-810
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• 1998

This paper presents BIST (Built-in self-test) techniques for detection of path delay faults in digital circuits. In the proosed BIST schemes, the shift registers make possible to concurrently generate and compact the latched test data. Therefore the test time is reduced efficiently. By reordering the elements of th shifte register based on the information of the hamming distance of each memory elements in CUt, it is possible to increase the number of path delay faults detected robustly/non-robustly. Experimental results for ISCAS'89 benchmark circuits show the efficiency of the proposed BIST techniques.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.819-822
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• 1998

The high complexity of digital circuits has changed the digital circuits design mehtods from schemeatic-based to hardware description languages like VHDL, verilog that make hardware faults become more hard to detect. Thus test generation to detect hardware defects is very important part of the design. But most of the test generation methods are gate-level based. In this paper new high-level test generation method to detect stuck-at-faults on gate level is described. This test generation method is independent of synthesis results and reduce the time and efforts for test generation.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.823-826
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• 1998

This paper addresses a characterization of fault effects in asynchronous circuits. A characterization has been performed on races caused by a single stuck-at faults (SSAF). The faults sometimes lead to races in faulty circuits, which prevent faults from observing and the circuit is insufficiently tested. To identify those obstacles, we have proposed non-detectable single stuck-at fault(NDSSAF) conditions and proposed an algorithm to find them. In the help of the proposed methodology, the asynchronous circuits can be fully SSAF testable.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.114-120
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• 1995

It is important to test the various kinds of interconnect faults between chips on a card/module. When boundary scan design techniques are adopted, the chip to chip interconnection test generation and application of test patterns is greatly simplified. Various test generation algorithms have been developed for interconnect faults. A new interconnect test generation algorithm is introduced. It reduces the number of test patterns by half over present techniques. It also guarantees the complete diagnosis of mutiple interconnect faults.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.5
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• pp.661-670
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• 1995

This paper presents a fast massively parallel automatic test pattern generator for digital combinational logic circuits using neural networks. Automatic test pattern generation neural network(ATPGNN) evolves its state to a stable local minima by exchanging messages among neural network modules. In preprocessing phase, we calculate the essential assignments for the stuck-at faults in fault list by adopting dominator concept. It makes more neurons be fixed and the system speed up. Consequently. fast test pattern generation is achieved. Test patterns for stuck-open faults are generated through getting initialization patterns for the obtained stuck-at faults in the corresponding ATPGNN.

• Proceedings of the KSPS conference
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• 2006.05a
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• pp.85-88
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• 2006

Generally the news subtitle is considered as be free of fault. But actually it has committed a fault in many respects. Among these I made a special study of phonological faults; alternation of graphemes, insertion of graphemes, deletion of graphemes and the orthography of loanwords. It is very surprising that the news subtitle has many faults against Korean orthography, We must try to get rid of the faults in the news subtitle.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.3
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• pp.161-165
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• 2004

In this paper, we have designed the ground faults detection and interrupting controller at normal condition of AC 120v to 240v rating voltage. Ground faults in electrical network have the characteristics of low current, 60㎐ frequency to 2㎑frequency. The load condition are no load and 20A load. The trip level of the controller is 6㎃ with ground faults. The Controller algorithm is implemented using pic16c71 microprocessor.