• 한국자동차공학회논문집
• /
• 제13권1호
• /
• pp.126-131
• /
• 2005

This paper presents experimental results by using the machinery fault simulator which is monitoring its conditions with an acceleration signal. Components of the machinery, for example, motor, belt pulley, belt, bearing, and gear, with artificial defects were used for the experiment.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2000년도 하계학술대회 논문집 D
• /
• pp.3192-3194
• /
• 2000

Many I/o cards such as AOCs, DICs, DOCs and ROCs are used to deal with I&C instruments of control panel in full-scope power plant simulator. To help the maintenance of I/O cards, an I/o card fault diagnosis system is implemented in this paper. The implemented fault diagnosis system has the automatic fault diagnosis function and manual card test function for fault diagnosis. Finally, the test result using I/O cards shows the validity of the implemented fault diagnosis system.

• 전자공학회논문지A
• /
• 제31A권4호
• /
• pp.116-126
• /
• 1994

In this paper, the switch-level fault simulator for CMOS circuits with a gate-to-drain/source short fault is implemented. A fault model used in this paper is based on the graphical analysis of the electrical characteristics of the faulty MOS devices and the conversion of the faulty CMOS circuit to the equivalent faulty CMOS inverter in order to find its effect on the successive stage. This technique is very simple and has the increased accuracy of the simulation. The simulation result of the faulty circuit using the implemented fault simulator is compared with the result of the SPICE simulation.

• 한국통신학회논문지
• /
• 제22권8호
• /
• pp.1823-1832
• /
• 1997

본 논문은 유한 상태 기계 모델로 표현된 통신 프로토콜의 시험항목에 대한 오류 발견 능력 분석 방법을 제시한다. 시험항목에 대한 오류 발견 능력의 평가는 생성된 시험항목으로 어느 정도까지 오류를 발견해 낼 수 있는지를 측정하는 것이다. 시험항복의 오류 발견 능력 평가 방법은 주로 수학적 분석과 시뮬레이션을 이용한 방법이 사용되고 있다. 본 논문에서는 동신 프로토콜 시험항목의 오류 발견 능력 분석음 위해 시뮬레이터를 설계, 구현하였다. Inres 프로토콜을 시뮬레이터에 적용한 결과, 출력 오류와 상태 병합. 분리 오류는 100%의 높은 오류 발견율을 보였다. 구현된 오류 발견 능력 분석 시뮬레이터는 다양한 프로토콜에 적용 가능함으로써 새로운 오류 발견 능력 분석 도구로 사용될 수 있다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1998년도 추계종합학술대회 논문집
• /
• pp.719-722
• /
• 1998

Fault simulation for large and complex sequential circuits is highly cpu-intensive task in the intergrated circuit design process. In this paper, we propose CM-SIM, a concurrent fault simulator which employs an optimal memory management strategy and simple list operations. CM-SIM removes inefficiencies and uses new dynamic memory management strategies, using contiguous array memory. Consequently, we got improved performance and reduced memory usage in concurrent fault simulation.

• ETRI Journal
• /
• 제33권1호
• /
• pp.50-59
• /
• 2011

In the current very deep submicron technology era, fault tolerant mechanisms perform an essential function to cope with the effects of soft errors. To evaluate the effectiveness of the fault tolerant mechanism, reliability engineers use simulated fault injections using either saboteur modules or mutants in the simulation model. However, the two methods suffer from both inefficiency in the simulation mechanism and difficulties with the experimental setups. To overcome these inefficiencies, we propose the Verilog-based simulated fault injection (VFI) technique. VFI has the following advantages. First, modification of the design model is unnecessary. Second, the fault injection simulation procedure is simple and efficient. Third, various types of fault injection experiments can be performed. To evaluate the effectiveness of the proposed methodology, we developed a VFI environment using the ICARUS Verilog Simulator. From the experimental results, we were able to qualitatively evaluate the reliability of the target simulation models and to assess the effectiveness of the employed fault-tolerance mechanisms.

• 한국압력기기공학회 논문집
• /
• 제13권1호
• /
• pp.48-53
• /
• 2017

We diagnosed the defect using the data obtained from the nuclear power plant simulator. In this paper, we diagnosed faults in the nuclear power plant system for discovery instead of the traditional single-component or device unit. We created the six fault scenarios and used a fault simulator to obtain the fault data. It was extracted pattern from acquired failure data. Neural network model was trained and simple pattern matching algorithm was applied. We presented a simulation result and confirmed that the applied algorithm works correctly.

• 한국정보처리학회논문지
• /
• 제4권1호
• /
• pp.298-310
• /
• 1997

스캔 환경에 바탕을 둔 대부분의 경로 지연고장 시뮬레이터들은 개선된 스캔 플 립플롭을 사용하며 일반적인 논리 게이트를 대상으로만 동작한다. 본 연구에서는 새 로운 논리값을 사용한 새로운 경로 지연고장 시뮬레이션 알고리즘을 고안하여 이의 적용범위를 CMOS 소자를 포함하는 대규모 집적회로로 확장하였다. 제안된 알고리즘에 기초하여 표준 스캔 환경 하에서 동작하는 고속 지연고장 시뮬레이터를 개발하였다. 실험결과는 새 시뮬레이터가 효율적이며 정확함을 보여준다.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 1997년도 한국자동제어학술회의논문집; 한국전력공사 서울연수원; 17-18 Oct. 1997
• /
• pp.341-344
• /
• 1997

This paper presents a dynamics failure detection algorithm developed for the two-motor-driven electric vehicle system. The algorithm is based on the application of the fault detection filter. The fault detection includes the identification of sudden pressure drops of the two rear tires in driving axis and dynamics faults of the two inverter-motor-paired actuators An E.V. dynamics simulator is developed, which includes the modeling of the E.V. dynamics as well as the driving dynamics. The simulator, which allows the generation of various fault situations, is utilized in the verification of the developed fault detection algorithm. The results of the simulations are also presented.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1997년도 하계학술대회 논문집 D
• /
• pp.936-938
• /
• 1997

Up to date, operator assistance systems -fault diagnosis system, fault restoration system etc.- are developed for power system automation. In this condition, an efficiency test of assistance system must be performed to prove application in real power system. This paper presents an SCADA simulator for an efficiency test of the operator assistance system, which is developed in the SCADA system. The proposed simulator is implemented under Win95 with Pentium-PC.