• Transactions of the Korean Society of Automotive Engineers
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• v.13 no.1
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• pp.126-131
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• 2005

This paper presents experimental results by using the machinery fault simulator which is monitoring its conditions with an acceleration signal. Components of the machinery, for example, motor, belt pulley, belt, bearing, and gear, with artificial defects were used for the experiment.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3192-3194
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• 2000

Many I/o cards such as AOCs, DICs, DOCs and ROCs are used to deal with I&C instruments of control panel in full-scope power plant simulator. To help the maintenance of I/O cards, an I/o card fault diagnosis system is implemented in this paper. The implemented fault diagnosis system has the automatic fault diagnosis function and manual card test function for fault diagnosis. Finally, the test result using I/O cards shows the validity of the implemented fault diagnosis system.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.116-126
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• 1994

In this paper, the switch-level fault simulator for CMOS circuits with a gate-to-drain/source short fault is implemented. A fault model used in this paper is based on the graphical analysis of the electrical characteristics of the faulty MOS devices and the conversion of the faulty CMOS circuit to the equivalent faulty CMOS inverter in order to find its effect on the successive stage. This technique is very simple and has the increased accuracy of the simulation. The simulation result of the faulty circuit using the implemented fault simulator is compared with the result of the SPICE simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1823-1832
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• 1997

In this ppaer, fault coverage analysis of a conformance test case for communication protocols, specified as a deterministic finite state machine(DFSM) is presented. The fault coverage analysis of a test case is defined by measuring the extent of the faults detected using a generated test case. The method that evaluates fault coverage analysis for a test case, has been researched by arithmetic analysis and simulation. In this paper, we designed and implemented a simulator for fault coverage analysis of a communication protocol teat case. With this result for Inres protocol, output fault and state merge and split fault have a high fault coverage of 100%. This simulator can be widely used with new fault coverage analysis tools by applying it to various protocols.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.719-722
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• 1998

Fault simulation for large and complex sequential circuits is highly cpu-intensive task in the intergrated circuit design process. In this paper, we propose CM-SIM, a concurrent fault simulator which employs an optimal memory management strategy and simple list operations. CM-SIM removes inefficiencies and uses new dynamic memory management strategies, using contiguous array memory. Consequently, we got improved performance and reduced memory usage in concurrent fault simulation.

• ETRI Journal
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• v.33 no.1
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• pp.50-59
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• 2011

In the current very deep submicron technology era, fault tolerant mechanisms perform an essential function to cope with the effects of soft errors. To evaluate the effectiveness of the fault tolerant mechanism, reliability engineers use simulated fault injections using either saboteur modules or mutants in the simulation model. However, the two methods suffer from both inefficiency in the simulation mechanism and difficulties with the experimental setups. To overcome these inefficiencies, we propose the Verilog-based simulated fault injection (VFI) technique. VFI has the following advantages. First, modification of the design model is unnecessary. Second, the fault injection simulation procedure is simple and efficient. Third, various types of fault injection experiments can be performed. To evaluate the effectiveness of the proposed methodology, we developed a VFI environment using the ICARUS Verilog Simulator. From the experimental results, we were able to qualitatively evaluate the reliability of the target simulation models and to assess the effectiveness of the employed fault-tolerance mechanisms.

• Transactions of the Korean Society of Pressure Vessels and Piping
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• v.13 no.1
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• pp.48-53
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• 2017

We diagnosed the defect using the data obtained from the nuclear power plant simulator. In this paper, we diagnosed faults in the nuclear power plant system for discovery instead of the traditional single-component or device unit. We created the six fault scenarios and used a fault simulator to obtain the fault data. It was extracted pattern from acquired failure data. Neural network model was trained and simple pattern matching algorithm was applied. We presented a simulation result and confirmed that the applied algorithm works correctly.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.298-310
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• 1997

Most of the available delay fault simulators for scan environments rely on the use of enhanced scan flip-flops and exclusively consider circuits composed of only discrete gates. In this research, a new path delay fault simulation algorithm using new logic values is devised to enlarge the scope to the VLSI circuits which consist of CMOS elements. Based on the proposed algorithm, a high speed path delay fault simulator for standard scan environments is developed. The experimental results show the new simulator is efficient and accurate.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.341-344
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• 1997

This paper presents a dynamics failure detection algorithm developed for the two-motor-driven electric vehicle system. The algorithm is based on the application of the fault detection filter. The fault detection includes the identification of sudden pressure drops of the two rear tires in driving axis and dynamics faults of the two inverter-motor-paired actuators An E.V. dynamics simulator is developed, which includes the modeling of the E.V. dynamics as well as the driving dynamics. The simulator, which allows the generation of various fault situations, is utilized in the verification of the developed fault detection algorithm. The results of the simulations are also presented.

• Proceedings of the KIEE Conference
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• 1997.07c
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• pp.936-938
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• 1997

Up to date, operator assistance systems -fault diagnosis system, fault restoration system etc.- are developed for power system automation. In this condition, an efficiency test of assistance system must be performed to prove application in real power system. This paper presents an SCADA simulator for an efficiency test of the operator assistance system, which is developed in the SCADA system. The proposed simulator is implemented under Win95 with Pentium-PC.