• 제목/요약/키워드: Fault Code

검색결과 123건 처리시간 0.025초

Reduction of Test Data and Power in Scan Testing for Digital Circuits using the Code-based Technique (코드 기반 기법을 이용한 디지털 회로의 스캔 테스트 데이터와 전력단축)

  • Hur, Yong-Min;Shin, Jae-Heung
    • 전자공학회논문지 IE
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    • 제45권3호
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    • pp.5-12
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    • 2008
  • We propose efficient scan testing method capable of reducing the test data and power dissipation for digital logic circuits. The proposed testing method is based on a hybrid run-length encoding which reduces test data storage on the tester. We also introduce modified Bus-invert coding method and scan cell design in scan cell reordering, thus providing increased power saving in scan in operation. Experimental results for ISCAS'89 benchmark circuits show that average power of 96.7% and peak power of 84% are reduced on the average without fault coverage degrading. We have obtained a high reduction of 78.2% on the test data compared the existing compression methods.

Computing Method for The Number of The Interaction Strength Based on Software Whitebox Testing (소프트웨어 화이트박스 테스트의 교호 강도 수 기반 테스트 방법)

  • Choi, Hyeong-Seob;Park, Hong-Seong
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • 제46권5호
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    • pp.29-36
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    • 2009
  • Cost and Time for software test is gradually increasing as the software complexity increases. To cope with this problem, it is very important to reduce the number of test cases used in the software test. The interaction strength number is especially important in decision of the number of test cases for the unit test, where the interaction strength number means the number of arguments which affect the results of a function by the analysis of their combination used in source code of the function. This paper proposes the algorithm that computes the number of the interaction strength, where analyzes the patterns used in the source code of a function and increase its number when the pattern matches one of the specified patterns. The proposed algorithm is validated by some experiments finding coverage and the number of fault detection.

A Study on the Structural Behavior of an Underground Radwaste Repository within a Granitic Rock Mass with a Fault Passing through the Cavern Roof (화장암반내 단층지역에 위치한 지하 방사성폐기물 처분장 구조거동연구)

  • 김진웅;강철형;배대석
    • Tunnel and Underground Space
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    • 제11권3호
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    • pp.257-269
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    • 2001
  • Numerical simulation is performed to understand the structural behavior of an underground radwaste repository, assumed to be located at the depth of 500 m, in a granitic rock mats, in which a fault intersects the roof of the repository cavern. Two dimensional universal distinct element code, UDEC is used in the analysis. The numerical model includes a granitic rock mass, a canister with PWR spent fuels surrounded by the compacted bentonite inside the deposition hole, and the mixed bentonite backfilled in the rest of the space within the repository cavern. The structural behavior of three different cases, each case with a fault of an angle of $33^{\circ},\;45^{\circ},\;and\;58^{\circ}$ passing through the cavern roof-wall intersection, has been compared. And then fro the case with the $45^{\circ}$ fault, the hydro-mechanical, thermo-mechanical, and thermo-hydro-mechanical interaction behavior have been studied. The effect of the time-dependent decaying heat, from the radioactive materials in PWR spent fuels, on the repository and its surroundings has been studied. The groundwater table is assumed to be located 10m below the ground surface, and a steady state flow algorithm is used.

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A Fault Tolerant ATM Switch using a Fully Adaptive Self-routing Algorithm - The Cyclic Banyan Network (실내 무선 통신로에서 파일럿 심볼을 삽입한 Concatenated FEC 부호에 의한 WATM의 성능 개선)

  • 박기식;강영흥;김종원;정해원;양해권;조성준
    • The Journal of Korean Institute of Communications and Information Sciences
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    • 제24권9A호
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    • pp.1276-1284
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    • 1999
  • We have evaluated the BER's and CLP's of Wireless ATM (WATM) cells employing the concatenated FEC code with pilot symbols for fading compensation through the simulation in indoor wireless channel modeled as a Rayleigh and a Rician fading channel, respectively. The results of the performance evaluation are compared with those obtained by employing the convolutional code in the same condition. In Rayleigh fading channel, considering the maximum tolerance BER ( $10^-3$) as a criterion of the voice service, it is blown that the performance improvement of about 4 dB is obtained in terms of $E_b/N_o$ by employing the concatenated FEC code with pilot symbols rather than the convolutional code with pilot symbols.When the values of K parameter which means the ratio of the direct signal to scattered signal power in Rician fading channel are 6 and 10, it is shown that the performance improvement of about 4 dB and 2 dB is obtained, respectively, in terms of $E_b/N_o$ by employing the concatenated FEC code with pilot symbols considering the maximum tolerance BER of the voice service. Also in Rician fading channel of K=6 and K= 10, considering CLP = $10^-3$ as a criterion, it is observed that the performance improvement of about 3.5 dB and1.5 dB is obtained, respectively, in terms of $E_b/N_o$ by employing the concatenated FEC code with pilot symbols.

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Secure methodology of the Autocode integrity for the Helicopter Fly-By-Wire Control Law using formal verification tool (정형검증 도구를 활용한 Fly-By-Wire 헬리콥터 비행제어법칙 자동코드 무결성 확보 방안)

  • An, Seong-Jun;Cho, In-Je;Kang, Hye-Jin
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • 제42권5호
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    • pp.398-405
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    • 2014
  • Recently the embedded software has been widely applied to the safety-critical systems in aviation and defense industries, therefore, the higher level of reliability, availability and fault tolerance has become a key factor for its implementation into the systems. The integrity of the software can be verified using the static analysis tools. And recent developed static analysis tool can evaluate code integrity through the mathematical analysis method. In this paper we detect the autocode error and violation of coding rules using the formal verification tool, Polyspace(R). And the fundamental errors on the flight control law model have been detected and corrected using the formal verification results. As a result of verification process, FBW helicopter control law autocode can ensure code integrity.

The efficient DC-link voltage design of the Type 4 wind turbine that satisfies HVRT function requirements (HVRT 기능 요구조건을 만족하는 Type 4 풍력 발전기의 효율적인 직류단 전압 설계)

  • Baek, Seung-Hyuk;Kim, Sungmin
    • Journal of IKEEE
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    • 제25권2호
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    • pp.399-407
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    • 2021
  • This paper proposes the DC-link voltage design method of Type 4 wind turbine that minimizes power loss and satisfies the High Voltage Ride Through(HVRT) function requirements of the transmission system operator. The Type 4 wind turbine used for large-capacity offshore wind turbine consists of the Back-to-Back converter in which the converter linked to the power grid and the inverter linked to the wind turbine share the DC-link. When the grid high voltage fault occurs in the Type 4 wind turbine, if the DC-link voltage is insufficient compared to the fault voltage level, the current controller of the grid-side converter can't operate smoothly due to over modulation. Therefore, to satisfy the HVRT function, the DC-link voltage should be designed based on the voltage level of high voltage fault. However, steady-state switching losses increase further as the DC-link voltage increases. Therefore, the considerations should be included for the loss to be increased when the DC-link voltage is designed significantly. In this paper, the design method for the DC-link voltage considered the fault voltage level and the loss is explained, and the validity of the proposed design method is verified through the HVRT function simulation based on the PSCAD model of the 2MVA Type 4 wind turbine.

A New Hardening Technique Against Radiation Faults in Asynchronous Digital Circuits Using Double Modular Redundancy (이중화 구조를 이용한 비동기 디지털 시스템의 방사선 고장 극복)

  • Kwak, Seong Woo;Yang, Jung-Min
    • Journal of Institute of Control, Robotics and Systems
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    • 제20권6호
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    • pp.625-630
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    • 2014
  • Asynchronous digital circuits working in military and space environments are often subject to the adverse effects of radiation faults. In this paper, we propose a new hardening technique against radiation faults. The considered digital system has the structure of DMR (Double Modular Redundancy), in which two sub-systems conduct the same work simultaneously. Based on the output feedback, the proposed scheme diagnoses occurrences of radiation faults and realizes immediate recovery to the normal behavior by overriding parts of memory bits of the faulty sub-system. As a case study, the proposed control scheme is applied to an asynchronous dual ring counter implemented in VHDL code.

A Regression Test Selection and Prioritization Technique

  • Malhotra, Ruchika;Kaur, Arvinder;Singh, Yogesh
    • Journal of Information Processing Systems
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    • 제6권2호
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    • pp.235-252
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    • 2010
  • Regression testing is a very costly process performed primarily as a software maintenance activity. It is the process of retesting the modified parts of the software and ensuring that no new errors have been introduced into previously tested source code due to these modifications. A regression test selection technique selects an appropriate number of test cases from a test suite that might expose a fault in the modified program. In this paper, we propose both a regression test selection and prioritization technique. We implemented our regression test selection technique and demonstrated in two case studies that our technique is effective regarding selecting and prioritizing test cases. The results show that our technique may significantly reduce the number of test cases and thus the cost and resources for performing regression testing on modified software.

Development of neural network algorithm for an advanced distributed control system (고급 분산 제어시스템을 위한 신경 회로망 제어 알고리즘의 개발)

  • 이승준;박세화;박동조;김병국;변증남
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1993년도 한국자동제어학술회의논문집(국내학술편); Seoul National University, Seoul; 20-22 Oct. 1993
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    • pp.953-958
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    • 1993
  • We develop a neural network control algorithm for the ACS (Advanced Control System). The ACS is an extended version of the DCS (Distributed Control System) to which functions of fault detection and diagnosis and advanced control algorithms are added such as neural networks, fuzzy logics, and so on. In spite of its usefulness proven by computer simulations, the neural network control algorithm, as far as we know, has no tool which makes it applicable to process control. It is necessary that the neural network controller should be turned into the function code for its application to the ACS. So we develop a general method to implement the neural network control systems for the ACS. By simulations using the simulator for the boiler of 'Seoul fire power plant unit 4', the methodology proposed in this paper is validated to have the applicability to process control.

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Reliability Analysis of Interleaved Memory with a Scrubbing Technique (인터리빙 구조를 갖는 메모리의 스크러빙 기법 적용에 따른 신뢰도 해석)

  • Ryu, Sang-Moon
    • Journal of Institute of Control, Robotics and Systems
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    • 제20권4호
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    • pp.443-448
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    • 2014
  • Soft errors in memory devices that caused by radiation are the main threat from a reliability point of view. This threat can be commonly overcome with the combination of SEC (Single-Error Correction) codes and scrubbing technique. The interleaving architecture can give memory devices the ability of tolerating these soft errors, especially against multiple-bit soft errors. And the interleaving distance plays a key role in building the tolerance against multiple-bit soft errors. This paper proposes a reliability model of an interleaved memory device which suffers from multiple-bit soft errors and are protected by a combination of SEC code and scrubbing. The proposed model shows how the interleaving distance works to improve the reliability and can be used to make a decision in determining optimal scrubbing technique to meet the demands in reliability.