• Journal of IKEEE
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• v.23 no.3
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• pp.800-804
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• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.

• 유체기계공업학회:학술대회논문집
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• 2005.12a
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• pp.318-323
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• 2005

To evaluate the accurate performance of turbomachinery, it is important to measure the unsteady flow phenomena downstream of the rotor blade. This paper presents the development of the fast-response total pressure probe for the measurement of the total pressure field at the exit of rotor and the result of measurement in a 1-stage axial turbine. The fast-response total pressure probe was fabricated by installing a fast-response pressure sensor near the head of a Kiel probe. And it measured the phase-lock averaged total pressure downstream of an 1-stage axial turbine. The developed probe successfully measured the accurate total pressure distribution at rotor exit and made possible to evaluate the loss distribution and the accurate performance of turbomachinery.

• Tribology and Lubricants
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• v.19 no.6
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• pp.349-356
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• 2003

A damper floating ring seal with round hole pattern surfaces is suggested for better leakage control. The flat plate test of the round hole pattern surfaces has been performed to yield an empirical friction factor model. The exact predictions of the lock­up position of the damper floating ring, the leakage performance, and the rotordynamic coefficients of the seal are necessary to evaluate the rotordynamic performance of the turbo pump unit. The governing equations including the empirical friction factor model for round hole pattern surfaces are solved by the Fast Fourier Transform method. The lock­up position, leakage flow rate, and rotordynamic coefficients are evaluated according to the geometric parameters of the damper floating ring seal. Theoretical results show that the damper floating ring seals yield less leakage and better rotordynamic stability than the floating ring seal with a smooth surface.

• The KSFM Journal of Fluid Machinery
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• v.4 no.3 s.12
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• pp.29-38
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• 2001

The floating ring seal has the ability of minimizing clearance without the rubbing phenomenon. It is often used in the turbo pump units of liquid rocket engines due to its superior leakage performance. The exact prediction of the lock-up position of the floating ring, the leakage performance, and the rotordynamic coefficients of the seal is necessary to evaluate the rotordynamic performance of the turbo pump unit. The governing equations(which are based on the Bulk-flow Model) we solved by the Fast Fourier Transform method. The lock-up position, leakage flow rate, and rotordynamic coefficients are evaluated according to the geometric parameters of the floating ring seal.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.90-96
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• 2006

A novel ${\Sigma}{\Delta}$ fractional-N PLL architecture for fast locking and fractional spur suppressing is proposed based on the capacitance scaling scheme. It changes the effective capacitance of loop filter (LF) by increasing and decreasing current to the capacitor via different paths with multiple charge pumps. The effective capacitance of loop filter (LF) can be scaled up/down depending on operating status while keeping LF capacitors small enough to be integrated into a single PLL chip. Fractional spurs suppressing have been achieved by reducing the magnitude of charge pump current when the PLL is in-lock without degrading fast locking characteristic. It has been simulated by HSPICE in a CMOS $0.35{\mu}m$ process, and shows flat locking time is less than $8{\mu}s$ with the small size of LF capacitors, 200pF and 17pF, and $2.8k{\Omega}$ resistor.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.37 no.5
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• pp.502-510
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• 2009

Laser Inertial Navigation System(LINS) consists of Ring Laser Gyroscopes(RLG) and accelerometers. RLG has a lock-in region in which there is zero output for input angular rates less than 0.1deg/sec. The lock-in region is generated by the imperfect mirrors in RLG. To avoid the lock-in region, sinusoidal motion which is called dither motion is applied on RLG. Therefore without the fault in LINS, the dither motion must be measured by RLG/accelerometer. In this paper, we propose the method to detect the fault of LINS through checking out whether or not the dither motion is always measured by RLG/accelerometer using the Fast Fourier Transformation(FFT) on the real time. The feasibility of the fault detection method proposed in this paper is verified through the stationary and van test.

• The KIPS Transactions:PartB
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• v.19B no.2
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• pp.127-134
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• 2012

Video digital door lock(VDDL) system detects people who access to the door and acquires the human image. Design considerations is that current consumption must be minimized by applying fast human detection algorithm because of battery-based operation. Since the digital door lock takes an image through a fixed camera, detection of a person based on background image leads to high degree of reliability. This paper deals with a single human detection algorithm suitable for VDDL with fulfilling these requirements such that it detects a moving object in an image, then identifies whether the object is a person or not using image processing. The proposed image processing algorithm consists of two steps: Firstly, it detects the human image region using both background image and skin color information. Secondly, it identifies the person using polar histogram based on proportional information of human body. Proposed algorithm is implemented in VDDL and is verified the performance through experiments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Proceedings of the KIEE Conference
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• 2004.11d
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• pp.93-96
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• 2004

In this paper, we analyzed the current limiting characteristics according to increase of source voltage in the flux-lock type high-Tc superconducting fault current limiter (SFCL). The flux-lock type SFCL consisted of two coils, which were wound in parallel each other through an iron core, and high-Tc superconducting (HTSC) element connected with coil 2 in series. The flux-lock type SFCL has the characteristics better in comparison with the resistive type SFCL because the fault current in the flux-lock type SFCL can be divided into two coils by the inductance ratio of coil 1 and coil 2. The fault current limiting operation of the flux-lock type SFCL can be different due to winding direction of the two coils. The winding method where the decrease of linkage flux between two coils in the accident happens is called the subtractive polarity winding and the winding method in case of the increase of linkage flux is called the additive polarity winding. The fault current limiting experiments according to the source voltage were performed for these two winding methods. Through the comparison and the analysis of the experimental data, we confirmed that the quench time was shorter, irrespective of the winding direction as the source voltage increased and that the fault current and the HTSC's resistance increased as the amplitude of the source voltage increased. The additive polarity winding made the fast quench time and the lower resistance of HTSC element in comparison with the subtractive polarity winding. The fault current of the subtractive polarity winding was larger than that of the additive polarity winding. In conclusion, we found that the additive polarity winding reduced the burden of SFCL because the quench time was shorter and the fault current was smaller than those of the subtractive polarity winding.

• ETRI Journal
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• v.28 no.4
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• pp.435-443
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• 2006

This paper presents an efficient carrier recovery algorithm combined with a turbo-coding technique in a mobile communication system. By using a block turbo code made up of independently decodable block codes, we can efficiently recover the fast time-varying carrier phase as well as correct channel errors. Our simulation results reveal that the proposed scheme can accommodate mobiles with high speed, and at the same time can reduce the number of iterations to lock the phase.