• Title/Summary/Keyword: Fast algorithm

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A method of searching the optimum performance of a classifier by testing only the significant events (중요한 이벤트만을 검색함으로써 분류기의 최적 성능을 찾는 방법)

  • Kim, Dong-Hui;Lee, Won Don
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.6
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    • pp.1275-1282
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    • 2014
  • Too much information exists in ubiquitous environment, and therefore it is not easy to obtain the appropriately classified information from the available data set. Decision tree algorithm is useful in the field of data mining or machine learning system, as it is fast and deduces good result on the problem of classification. Sometimes, however, a decision tree may have leaf nodes which consist of only a few or noise data. The decisions made by those weak leaves will not be effective and therefore should be excluded in the decision process. This paper proposes a method using a classifier, UChoo, for solving a classification problem, and suggests an effective method of decision process involving only the important leaves and thereby excluding the noisy leaves. The experiment shows that this method is effective and reduces the erroneous decisions and can be applied when only important decisions should be made.

A Study on the Postprocessing of Channel Estimates in LTE System (LTE 시스템 채널 추정치의 후처리 기법 연구)

  • Yoo, Kyung-Yul
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.1
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    • pp.205-213
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    • 2011
  • The Long Term Evolution (LTE) system is designed to provide a high quality data service for fast moving mobile users. It is based on the Orthogonal Frequency Division Multiplexing (OFDM) and relies its channel estimation on the training samples which are systematically built within the transmitting data. Either a preamble or a lattice type is used for the distribution of training samples and the latter suits better for the multipath fading channel environment whose channel frequency response (CFR) fluctuates rapidly with time. In the lattice-type structure, the estimation of the CFR makes use of the least squares estimate (LSE) for each pilot samples, followed by an interpolation both in time-and in frequency-domain to fill up the channel estimates for subcarriers corresponding to data samples. All interpolation schemes should rely on the pilot estimates only, and thus, their performances are bounded by the quality of pilot estimates. However, the additive noise give rise to high fluctuation on the pilot estimates, especially in a communication environment with low signal-to-noise ratio. These high fluctuations could be monitored in the alternating high values of the first forward differences (FFD) between pilot estimates. In this paper, we analyzed statistically those FFD values and propose a postprocessing algorithm to suppress high fluctuations in the noisy pilot estimates. The proposed method is based on a localized adaptive moving-average filtering. The performance of the proposed technique is verified on a multipath environment suggested on a 3GPP LTE specification. It is shown that the mean-squared error (MSE) between the actual CFR and pilot estimates could be reduced up to 68% from the noisy pilot estimates.

A Novel Control Strategy of Three-phase, Four-wire UPQC for Power Quality Improvement

  • Pal, Yash;Swarup, A.;Singh, Bhim
    • Journal of Electrical Engineering and Technology
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    • v.7 no.1
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    • pp.1-8
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    • 2012
  • The current paper presents a novel control strategy of a three-phase, four-wire Unified Power Quality (UPQC) to improve power quality. The UPQC is realized by the integration of series and shunt active power filters (APF) sharing a common dc bus capacitor. The realization of shunt APF is carried out using a three-phase, four-leg Voltage Source Inverter (VSI), and the series APF is realized using a three-phase, three-leg VSI. To extract the fundamental source voltages as reference signals for series APF, a zero-crossing detector and sample-and-hold circuits are used. For the control of shunt APF, a simple scheme based on the real component of fundamental load current (I $Cos{\Phi}$) with reduced numbers of current sensors is applied. The performance of the applied control algorithm is evaluated in terms of power-factor correction, source neutral current mitigation, load balancing, and mitigation of voltage and current harmonics in a three-phase, four-wire distribution system for different combinations of linear and non-linear loads. The reference signals and sensed signals are used in a hysteresis controller to generate switching signals for shunt and series APFs. In this proposed UPQC control scheme, the current/voltage control is applied to the fundamental supply currents/voltages instead of fast-changing APF currents/voltages, thus reducing the computational delay and the required sensors. MATLAB/Simulink-based simulations that support the functionality of the UPQC are obtained.

The Design of High-Speed, High-Resolution D/A Converter for Digital Image Signal Processing with Deglitching Current Cell (글리치 방지 전류원을 이용한 고속 고정밀 디지탈 영상 신호 처리용 D/A 변환기 설계)

  • Lee, Seong-Dae;Jeong, Gang-Min
    • The Transactions of the Korea Information Processing Society
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    • v.1 no.4
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    • pp.469-478
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    • 1994
  • In this paper, a high speed, high resolution information processing digital- analog converter was designed for high definition color graphic, digital image signal processing, HDTV. For high speed operation, matrix type current cell array, latch which is not use pipelined, and two dimensional structure decoder using transmission gate were designed. It is adopted to fast-conversion, low-power implementation and exhibited high performance at linearity and accuracy. To reduce silicon area and to maintain resolution, current cell array composed of weighted and non-weighted current cells. In this paper, deglitching current cell design for high accuracy, new switching algorithm assert to reduce switching error. It's This circuit dissipates 130W with a 5-V power supply, and operate above 100MHz with 10 bit resolution.

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A Fast MB Mode Selection Algorithm in the H.264 Standard (H.264에서의 고속 매크로블록 모드 선택 알고리듬)

  • Kim Donghyung;Jeong Jechang
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.1C
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    • pp.61-72
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    • 2005
  • For the improvement of coding efficiency, the H.264 standard uses new coding tools such as VBS, 1/4-pel accurate ME, multiple references, intra prediction, loop filter, etc. Using these coding tools, H.264 has achieved significant improvements from rate-distortion point of view compared to existing standards. However, the encoder complexity is greatly increased due to these coding tools. We focus on the complexity reduction method of MB mode selection. Among all modes which can be selected, $8{\times}8$ and intra $4{\times}4$ mode have higher complexity than the others. So we propose the methods for reduction of the $8{\times}8$ and intra $4{\times}4$ mode complexity by using information of other modes with relatively low complexity. Simulation results show that the proposed methods save up to $54.6{\%}$ of total encoding time while keeping the average decrease about 0.012dB in PSNR.

Static Analysis of Frame Structures Using Transfer of Stiffness Coefficient (강성계수의 전달을 이용한 골조구조물의 정적해석)

  • 최명수;문덕홍;정하용
    • Journal of the Computational Structural Engineering Institute of Korea
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    • v.16 no.1
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    • pp.9-18
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    • 2003
  • In static analysis of a variety of structures, the matrix method of structural analysis is the most widely used and powerful analysis method. However, this method has drawback requiring high-performance computers with many memory units and fast processing units in the case of analyzing accurately structures with a large number of degrees-of- freedom. Therefore, it's very difficult to analyze these structures accurately in personal computers. For overcoming the drawback of the matrix method of structural analysis, authors suggest the transfer stiffness coefficient method(TSCM). The TSCM is very suitable to a personal computer because the concept of the TSCM is based on the transfer of the stiffness coefficient for an analytical structure. In this paper, the static analysis algorithm for frame structures is formulated by the TSCM. We confirm the validity of the TSCM through the comparison of computation results by the TSCM, the NASTRAN, the matrix method of structural analysis and the analytical solution.

Optical CBC Block Encryption Method using Free Space Parallel Processing of XOR Operations (XOR 연산의 자유 공간 병렬 처리를 이용한 광학적 CBC 블록 암호화 기법)

  • Gil, Sang Keun
    • Korean Journal of Optics and Photonics
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    • v.24 no.5
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    • pp.262-270
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    • 2013
  • In this paper, we propose a modified optical CBC(Cipher Block Chaining) encryption method using optical XOR logic operations. The proposed method is optically implemented by using dual encoding and a free-space interconnected optical logic gate technique in order to process XOR operations in parallel. Also, we suggest a CBC encryption/decryption optical module which can be fabricated with simple optical architecture. The proposed method makes it possible to encrypt and decrypt vast two-dimensional data very quickly due to the fast optical parallel processing property, and provides more security strength than the conventional electronic CBC algorithm because of the longer security key with the two-dimensional array. Computer simulations show that the proposed method is very effective in CBC encryption processing and can be applied to even ECB(Electronic Code Book) mode and CFB(Cipher Feedback Block) mode.

Implementation of Pattern Generator for Efficient IDDQ Test Generation in CMOS VLSI (CMOS VLSI의 효율적인 IDDQ 테스트 생성을 위한 패턴 생성기의 구현)

  • Bae, Seong-Hwan;Kim, Gwan-Ung;Jeon, Byeong-Sil
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.4
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    • pp.292-301
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    • 2001
  • IDDQ Testing is a very effective testing method to detect many kinds of physical defects occurred in CMOS VLSI circuits. In this paper, we consider the most commonly occurring bridging faults in current CMOS technologies and develop pattern generator for IDDQ testing using efficient IDDQ test algorithms. The complete set of bridging faults between every pair of all nodes(internal and external nodes) within circuit under test is assumed as target fault model. The merit of considering the complete bridging fault set is that layout information is not necessary. Implemented test pattern generator uses a new neighbor searching algorithm and fault collapsing schemes to achieve fast run time, high fault coverage, and compact test sets. Experimental results for ISCAS benchmark circuits demonstrate higher efficiency than those of previous methods.

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Facial Detection using Haar-like Feature and Bezier Curve (Haar-like와 베지어 곡선을 이용한 얼굴 성분 검출)

  • An, Kyeoung-Jun;Lee, Sang-Yong
    • Journal of Digital Convergence
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    • v.11 no.9
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    • pp.311-318
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    • 2013
  • For face detection techniques, the correctness of detection decreases with different lightings and backgrounds so such requires new methods and techniques. This study has aimed to obtain data for reasoning human emotional information by analyzing the components of the eyes and mouth that are critical in expressing emotions. To do this, existing problems in detecting face are addressed and a detection method that has a high detection rate and fast processing speed good at detecting environmental elements is proposed. This method must detect a specific part (eyes and a mouth) by using Haar-like Feature technique with the application of an integral image. After which, binaries detect elements based on color information, dividing the face zone and skin zone. To generate correct shape, the shape of detected elements is generated by using a bezier curve-a curve generation algorithm. To evaluate the performance of the proposed method, an experiment was conducted by using data in the Face Recognition Homepage. The result showed that Haar-like technique and bezier curve method were able to detect face elements more elaborately.

A Gridless Area Router for Multichip Module Design (다중칩 모듈 설계를 위한 Gridless 배선기)

  • Lee, Tae-Sun;Rim, Chong-Suck
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.9
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    • pp.28-43
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    • 1999
  • In this paper, we present a gridless router for MultiChip Modules (MCM). Because our router uses corner stitching data structures, not a routing grid, to represent the routings status, it allows arbitrary location of pins, and routes variable-width wires, without a considerable waste of area from bulky vias. A routing speed is a very important factor because a gridless routing approach is known its computation is hard and complex, and MCM routing problem has so large routing area and layers. Our router completes the routing faster than the most of previously reported grid-based routers, with comparable routing result, by using SEGRAs routing algorithm whose very fast speed is proved, and the characteristics of the effective data structure.

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