• The Korean Journal of Malacology
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• v.6 no.1
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• pp.1-10
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• 1990

The occurrence of the larvae, the size of the spats daily attached to the collectors, the difference of the spat size with temperature, and the darly growth of a mussel, Mytilus edulis, were investigated at the off Songpo, Chinhae Bay, the southern part of Korea during the period from March 1 to August 30 in 1986. The water timperature and specific gravity ranged from 7.0 $^{\circ}C$ to 27.4$^{\circ}C$ (mean 17,24$\pm$5.9$0^{\circ}C$), and from 1.0126 to 1.0126(mean, 1.0242$\pm$0.0023), respectively. D-shaped larvae had two peak occurrences in March 8, April 19, Umbo-shaped larvad three peaks in March 8, April 21 and June 17, and full grown larvae two peaks in May 13 and June 23, respectively. Therefore, it is assumed that the mussel had two mass spawning time in early March and mid April and two mass settling time in mid May and alte June. The maximum size of the planktonic mussel larvae ranged from 375-400${\mu}{\textrm}{m}$ and most larvae sizing below 300${\mu}{\textrm}{m}$ long settled in adquate substrate. Spats just after settlement had the range from 26.5 to 547.3${\mu}{\textrm}{m}$ with the minimum of 225.0 ${\mu}{\textrm}{m}$ in mean shell length. The spats settled in summer season, when the water temperature raised above $25^{\circ}C$, were smaller than those settled in spring season in mean shell length. The early growth of the mussel spat had been assumed considerably fast.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.274-286
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• 2016

This paper presents a 4-channel multi-rate vertical-cavity surface-emitting laser (VCSEL) driver. In order to keep the output power constant with respect to the process, voltage, temperature (PVT) variations, this research proposes automatic power and magnitude. For the fast settling time, the high-speed 10-bit time-interleaved Flash-successive approximation analog to digital converter (Flash-SAR ADC) is proposed and shared for automatic power and magnitude calibration to reduce the die area and power consumption. This chip is fabricated using $0.13-{\mu}m$ CMOS technology and the die area is $4.2mm^2$. The power consumption is 117.84 mW per channel from a 3.3 V supply voltage at 10 Gbps. The measured resolution of bias /modulation current for APC/AMC is 0.015 mA.

• 대한공업교육학회지
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• v.31 no.2
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• pp.364-380
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• 2006

This paper presents a procedure for designing command to maneuver flexible structure with very little residual vibration, even in the presence of modeling errors. For the open loop maneuver, the various shaped profiles using multiple step inputs delayed in time are considered for robustness and compared with the responses of rigid body and flexible body in virtue of simulations and experiments. Input shaping generates vibration-reducing shaped commands through convolution of an impulse sequence with the desired command. A flexible model with a cylindrical hub and four symmetric appendages is considered to examine the responses to real plant, and to illustrate the effectiveness of the proposed shapers. The appendages are long and flexible, leading to low frequency vibration under any control action. It is shown by a series of simulation that a properly designed feedback controller with input shaper performs well, as compared with open loop controller with input shaper. The control objective is to achieve a fast settling time of residual vibration to flexible structure and robustness (insensitivity)to plant uncertainty, to eliminate residual vibration.

• Journal of IKEEE
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• v.23 no.3
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• pp.800-804
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• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.

• Journal of Navigation and Port Research
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• v.47 no.2
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• pp.75-84
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• 2023

Ships need to ensure safety during their navigation, which makes route determination highly important. It must be accompanied by a route following controller that can accurately follow the route. This study proposes a method for automatically generating the ship route based on deep reinforcement learning algorithm and following it using a route following controller. To generate a ship route, under keel clearance was applied to secure the ship's safety and navigation chart information was used to apply ship navigation related regulations. For the experiment, a target ship with a draft of 8.23 m was designated. The target route in this study was to depart from Busan port and arrive at the pilot boarding place of the Ulsan port. As a route following controller, a velocity type fuzzy P ID controller that could compensate for the limitation of a linear controller was applied. As a result of using the deep Q network, a route with a total distance of 62.22 km and 81 waypoints was generated. To simplify the route, the Douglas-Peucker algorithm was introduced to reduce the total distance to 55.67 m and the number of way points to 3. After that, an experiment was conducted to follow the path generated by the target ship. Experiment results revealed that the velocity type fuzzy P ID controller had less overshoot and fast settling time. In addition, it had the advantage of reducing the energy loss of the ship because the change in rudder angle was smooth. This study can be used as a basic study of route automatic generation. It suggests a method of combining ship route generation with the route following control.

• The Sea:JOURNAL OF THE KOREAN SOCIETY OF OCEANOGRAPHY
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• v.9 no.1
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• pp.1-12
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• 2004

Sedimentary facies and high-resolution echo facies were analyzed to elucidate sedimentation pattern of the late Quaternary glacial-marine deposits in the northern continental margin of the South Shetland Islands. Six sedimentary facies are classified, based on grain texture and sedimentary structures in gravity cores. The high-resolution (3.5 ㎑) echo characters are classified into 6 echo facies on the basis of clarity, continuity, and shape of bottom and subbottom echoes together with seafloor topography. Distribution of the echo and sedimentary facies suggest that there was a significant change in sedimentation pattern between the Last Glacial Maximum (LGM) and subsequent glacier-retreating period. When the grounded glaciers extended to the present shelfbreak during LGM, coarse-grained subglacial tills were widespread in the shelf area, and deep troughs in the shelf were carved beneath the fast-flowing ice steam. As the glacial margin retreated landward after LGM, dense meltwater plumes released from the retreating ice-front were funneled along the glacier-carved troughs, and accumulated channel- or cannyon-fill deposits in the shelf and the upper to mid slope. At that time, slope sediments seem to have been reworked by slope failures and unsteady contour currents, and further transported by fine-grained turbidity currents along the South Shetland Trench. After the glacial retreat, sediments in the shelf and slope areas have been mainly introduced by persistent (hemi) pelagic settling, and fine-grained turbidity currents frequently occur along the axis of the South Shetland Trench.

• Textile Coloration and Finishing
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• v.17 no.2 s.81
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• pp.31-39
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• 2005

This study was conducted to remove the dyes in dye wastewater by the chemical precipitation or biological treatment which are one of the main pollutants in dye wastewater. In order to remove the disperse dyes effectively in aqueous solution by chemical precipitation process, coagulation and flocculation tests were carried out using several coagulants on various reaction conditions. It was found that the Ferrous sulfate was the most effective coagulant for the removal of disperse dye(DB79), and we could get the best result for the removal of disperse dye(DB56) in the aspects of TOC removal efficiency and sludge yield. When the Ferrous sulfate dosage was 800mg/l, the sludge settling velocity was very fast$(SV_{30}=4\%)$, and the color was effectively removed in the disperse dye(DB79) solution. Although the color removal was ineffective when the Alum was used as a coagulant, the sludge yield decreased in comparison with the Ferrous sulfate or the Ferric sulfate being used in the disperse dye(DB56) solution. In order to decolorize disperse dye(DR17) by using biological treatment process, a strain which has potential ability to degrade disperse dyes was isolated from natural system. The optimal culture conditions of temperature and pH were found to be $40^{\circ}C\;and\;8.5\~9$, respectively. When yeast extract was mixed with polypeptone at the mixing ratio of 1:1 as a nitrogen source, decolorization efficiency was highest$(93\%)$ among the nitrogen sources. The strain screened was excellent to adjust to pH, and it seems to have ability to control pH needed to growth. The optimal culture conditions in concentration of $MgSO_{4.}\cdot7H_2O\;and\;KH_2PO_4$ were $0.1\%(w/v)\;and\;0.2\%(w/v)$, respectively. Strains degrading and decolorizing reactive dyes, RB198 and RR141 which were isolated from water system, are named RBK1 and RRK. And the cell growth characteristics of RBK1 and RRK were investigated. The optimal culture conditions of temperature and pH were found to be 30t' and 7.0, respectively. Optimum nitrogen source was peptone, and it was found that decolorization efficiencies by strains RBK1 and RRK, were $85\%\;and\;62\%$, respectively, with introduction of 4,000mg/l of peptone. In the case of RBK1, color removal efficiencies were very high below 400mg/l. Decolorization efficiency was over $90\%$ at 20hours of culture time. The Color degradation ability of RRK was lower than that of RBK1.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.62-68
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• 2010

This work proposes a 10b 100MS/s DAC based on a segmented local matching technique primarily for small chip area. The proposed DAC employing a segmented current-steering structure shows the required high linearity even with the small number of devices and demonstrates a fast settling behavior at resistive loads. The proposed segmented local matching technique reduces the number of current cells to be matched and the size of MOS transistors while a double-cascode topology of current cells achieves a high output impedance even with minimum sized devices. The prototype DAC implemented in a 0.13um CMOS technology occupies a die area of $0.13mm^2$ and drives a $50{\Omega}$ load resistor with a full-scale single output voltage of $1.0V_{p-p}$ at a 3.3V power supply. The measured DNL and INL are within 0.73LSB and 0.76LSB, respectively. The maximum measured SFDR is 58.6dB at a 100MS/s conversion rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.56-63
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• 2010

This work proposes a 12b 100MS/s 0.13um CMOS pipeline ADC for battery-powered mobile video applications such as DVB-Handheld (DVB-H), DVB-Terrestrial (DVB-T), Satellite DMB (SDMB), and Terrestrial DMB (TDMB) requiring high resolution, low power, and small size at high speed. The proposed ADC employs a three-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. A single shared and switched op-amp for two MDACs removes a memory effect and a switching time delay, resulting in a fast signal settling. A two-step reference selection scheme for the last-stage 6b FLASH ADC reduces power consumption and chip area by 50%. The prototype ADC in a 0.13um 1P7M CMOS technology demonstrates a measured DNL and INL within 0.40LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 60.0dB and a maximum SFDR of 72.4dB at 100MS/s, respectively. The ADC with an active die area of 0.92 $mm^2$ consumes 24mW at 1.0V and 100MS/s. The FOM, power/($f_s{\times}2^{ENOB}$), of 0.29pJ/conv. is the lowest of ever reported 12b 100MS/s ADCs.

• Journal of Navigation and Port Research
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• v.32 no.6
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• pp.459-464
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• 2008

In this paper, we present the model-based fuzzy controller for container cranes which effectively performs set-point tracking control of trolley and anti-swaying control under system parameter and disturbance changes. The first part of this paper focuses on the development of Takagi-Sugeno (T-S) fuzzy modeling in a nonlinear container crane system. Parameters of the membership functions are adjusted by a RCGA to have same dynamic characteristics with nonlinear model of a container crane. In the second part, we present a design methodology of the model-based fuzzy controller. Sub-controllers are designed using LQ control theory for each subsystem in fuzzy model and then the proposed controller is performed with the combination of these sub-controllers by fuzzy IF-THEN rules. In the results of simulation, the fuzzy model showed almost similar dynamic characteristics compared to the outputs of the nonlinear container crane model. Also, the model-based fuzzy controller showed not only the fast settling time for the change in parameter and disturbance, but also stable and robust control performances without any steady-state error.