• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
• /
• v.24 no.2
• /
• pp.23-34
• /
• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• Journal of the Semiconductor & Display Technology
• /
• v.17 no.4
• /
• pp.42-45
• /
• 2018

As The semiconductor decrease from 10 nanometer to 7 nanometer, It is suggested that "More than Moore" is needed to follow Moore's Law, which has been a guide for the semiconductor industry. Fan-Out Wafer Level Package(FOWLP) is considered as the key to "More than Moore" to lead the next generation in semiconductors, and the reasons are as follows. the fan-out WLP does not require a substrate, unlike conventional wire bonding and flip-chip bonding packages. As a result, the thickness of the package reduces, and the interconnection becomes shorter. It is easy to increase the number of I / Os and apply it to the multi-layered 3D package. However, FOWLP has many issues that need to be resolved in order for mass production to become feasible. One of the most critical problem is the warpage problem in a process. Due to the nature of the FOWLP structure, the RDL is wired to multiple layers. The warpage problem arises when a new RDL layer is created. It occurs because the solder ball reflow process is exposed to high temperatures for long periods of time, which may cause cracks inside the package. For this reason, we have studied warpage in the FOWLP structure using commercial simulation software through the implementation of the reflow process. Simulation was performed to reproduce the experiment of products of molding compound company. Young's modulus and poisson's ratio were found to be influenced by the order of influence of the factors affecting the distortion. We confirmed that the lower young's modulus and poisson's ratio, the lower warpage.

• Information and Communications Magazine
• /
• v.28 no.11
• /
• pp.24-30
• /
• 2011

본고에서는 소형 고집적 이동단말기용 패키지를 위해 구현 되고 있는 능/수동소자 내장형 패키지 기술에 대해 알아보고자 한다. 능/수동소자내장형 패키지 기술은 IC 칩과 같은 능동 소자와 저항, 커패시터, 인덕터와 같은 수동소자 부품들을 패키지 기판 내부에 내장시켜 소형화를 추구함과 더불어 칩과 수동소자간의 접속 길이를 짧게 해서 전기적 성능을 향상시키실 수 있는 패키징 기술이다. 본 원고에서는 PCB기술에 기반을 둔 embedded active device 기술과 웨이퍼 레벨 패키징 기술에 기반을 둔 fan-out embedded wafer level package 기술 동향에 대해 서술하고 그 특정들을 비교 분석하였으며 이 기술들에 대환 동향을 살펴보고자 한다.

• Journal of the Microelectronics and Packaging Society
• /
• v.30 no.2
• /
• pp.52-59
• /
• 2023

The effects of dielectric curing temperature and temperature/humidity treatment conditions on the interfacial adhesion energies between Ti diffusion barrier/polybenzoxazole (PBO) dielectric layers were systematically investigated for Cu redistribution layer applications of fan-out wafer level package. The initial interfacial adhesion energies were 16.63, 25.95, 16.58 J/m² for PBO curing temperatures at 175, 200, and 225 ℃, respectively. X-ray photoelectron spectroscopy analysis showed that there exists a good correlation between the interfacial adhesion energy and the C-O peak area fractions at PBO delaminated surfaces. And the interfacial adhesion energies of samples cured at 200 ℃ decreased to 3.99 J/m² after 500 h at 85 ℃/85 % relative humidity, possibly due to the weak boundary layer formation inside PBO near Ti/PBO interface.