• Title/Summary/Keyword: Failsafe

Search Result 11, Processing Time 0.025 seconds

A Study on the Clamping Force Estimation and Failsafe Control Algorithm Design of the Electronic Wedge Brake System (Electronic Wedge Brake 시스템의 클램핑력 추정 및 Failsafe 제어 알고리즘 설계에 관한 연구)

  • Chung, Seunghwan;Lee, Hyeongcheol
    • Transactions of the Korean Society of Automotive Engineers
    • /
    • v.24 no.1
    • /
    • pp.16-23
    • /
    • 2016
  • The EWB(electronic wedge brake) is one in which the braking force is developed in a wedge and caliper system and applied to a disk and wedge mechanism. The advantage of the wedge structure is that it produces self-reinforcing effect and hence, utilizes minimal motor power, resulting in reduced gear and current. The extent of use of clamping force sensors and protection from failure of the EWB system directly depends on the level of vehicle mass production. This study investigated the mathematical equations, simulation modeling, and failsafe control algorithm for the clamping force sensor of the EWB and validated the simulations. As this EWB system modeling can be applied to motor inductance, resistance, screw inertia, stiffness, and wedge mass and angle, this study could improve the accuracy of simulation of the EWB. The simulation results demonstrated the braking force, motor speed, and current of the EWB system when the driver desired to the step and pulse the brake force inputs. Moreover, this paper demonstrated that the proposed failsafe control algorithm accurately detects faults in the clamping force sensor, if any.

Motion Sensor Fault Detection and Failsafe Logic for Vehic1e Stability Control Systems (VSCs)

  • Yi, Kyongsu;Min, Kyongchan
    • Journal of Mechanical Science and Technology
    • /
    • v.18 no.11
    • /
    • pp.1961-1968
    • /
    • 2004
  • The design of a reliable and failsafe control system requires that sensor failures be detected and identified within acceptable time limit so that system malfunction can be prevented. This paper presents a model-based approach to sensor fault detection with applications to vehicle stability control systems. The effectiveness of the proposed method is illustrated through test data-based evaluation. Vehicle test data-based evaluation results show that the proposed fault management scheme can be used for the design of a failsafe VSCs.

Failsafe Logic for a vehicle Stability Control System (차량 주행안정성 제어시스템의 자동안전 로직)

  • Min, Kyung-Chan;Lee, Gun-Bok;Yi, Kyoung-Su
    • Transactions of the Korean Society of Mechanical Engineers A
    • /
    • v.28 no.11
    • /
    • pp.1685-1691
    • /
    • 2004
  • This paper describes the fault detection and failsafe logic to be used in an Electronic Stability Program(ESP). The aim of this paper is to prevent of erroneous controls in the ESP. Developed this paper introduces the fault detection logic and evaluation of residual signals. The failsafe logic consists of four redundant sub-models, which can be used for detecting the faults in various sensors (yaw rate, lateral acceleration, steering wheel angle). We present two mathematical residual generation methods : one is a method using the average value and the other is a method using the minimum value of the each residual. We verified a failsafe logic developed using vehicle test results also we compare vehicle model based simulation results with test vehicle results.

Model-Based Fault Detection and Failsafe Logic Development (지능화 차량의 고장진단 로직 개발)

  • Min, Kyong-Chan;Kim, Jung-Tae;Lee, Gun-Bok;Lee, Kyong-Su
    • Proceedings of the KSME Conference
    • /
    • 2004.04a
    • /
    • pp.774-779
    • /
    • 2004
  • This paper describes the fault detection and failsafe logic to be used in the Electronic Stability Program (ESP). The Aim of this paper is prevention of erroneous control in the ESP. This paper introduces the fault detection logic and evaluation of residual signals. Failsafe logic consist of four redundant sub-models and they can be used for the detection of faults in each sensor (yaw rate, lateral acceleration, steering wheel angle). We presents two mathematical residual generation method ; one is the method by the average value, and the other is the method by the minimum value of the each residual. We verify a failsafe logic using vehicle test results, also we compare vehicle model based simulation results with test vehicle results.

  • PDF

Analysis of Diagnosis and Failsafe Algorithm Using Transmission Simulator (변속기 시뮬레이터를 이용한 진단 및 안전작동 알고리즘 분석)

  • Jung, Gyuhong
    • Transactions of the Korean Society of Automotive Engineers
    • /
    • v.22 no.4
    • /
    • pp.89-97
    • /
    • 2014
  • As the digital control technologies in automotive industry have advanced, electronic control units(ECUs) play a key-role to improve system performance. Transmission control unit(TCU) is a shifting controller for automatic transmission of which major functions are to determine the shift and manage the shifting process considering the various sensor signal on transmission and driver's commands. As with any ECU in vehicle, TCU performs complex algorithms such as shift control, diagnostic and failsafe functions. However, firmware design analysis is hardly possible by the reverse engineering due to code protection. Transmission simulator is a hardware-in-the-loop simulator which enables TCU to work in normal mode by simulating the electrical signal of TCU interface. In this research, diagnosis and failsafe algorithm implemented on commercialized TCU is analyzed by using the transmission simulator that is developed for wheel loader construction vehicle. This paper gives various experimental results on the proportional solenoid current trajectories for different operating modes, error detection criterion and limphome mode gears for all the possible cases of clutch malfunction. The derived results for conventional TCU can be applied to the development of inherent TCU algorithms and the transmission simulator can also be utilized for the test of TCU to be developed.

DESIRABLE PARAMETER IDENTIFICATION FOR THE IMPLEMENTATION OF IDEAL PASSIVE FAULT CURRENT LIMITER FOR THE PROTECTION OF POWER SEMICONDUCTOR DEVICES

  • Mukhopadhyay, S.C.;Iwahara, M.;Yamada, S.;Dawson, F.P.
    • Proceedings of the KIPE Conference
    • /
    • 1998.10a
    • /
    • pp.859-864
    • /
    • 1998
  • Compact and small size, reliable and failsafe operation and low cost featuring fault current limiter causing the designer to take a close look into the use of passive fault current limiter(FCL) for the protection of power semiconductor devices in power electronic systems. This paper has identified the main parameters responsible for the development of ideal passive magnetic current limiter. The effect of those parameters on the range of operation and the voltage-current characteristics of the magnetic current limiter has been studied using tableau approach. Desirable characteristics are discussed and the simulation results are presented.

  • PDF

Design of a New Key Escrow System (새로운 키 위탁 시스템의 설계)

  • Hwang, Bo-Seong;Lee, Im-Yeong
    • Journal of KIISE:Computer Systems and Theory
    • /
    • v.27 no.10
    • /
    • pp.840-847
    • /
    • 2000
  • 암호 시스템에서 가장 중요한 정보는 키 정보이다. 그러므로 공개 네트워크 상에서 비밀키의 관리는 아주 중요하다. 키가 손상되거나 유실되면 모든 정보가 유실되기 때문이다. 키 위탁 시스템이란 유사시의 상황에 대비해서 키를 특정한 위탁기관에 위탁함으로써 정보를 암호의 오용이나 키의 분실로부터 보호할 수 있는 시스템이다. 이러한 키 위탁 시스템을 이용함으로써 사용자의 키 유실이나 정보의 법 집행능력 확보를 제공할 수 있다. 일빈적으로 키 위탁 시스템은 사용자와 정부사이의 요구사항들이 상충에 의해 많은 무제를 가지고 있어 기존에 발표된 카 위탁 시스템은 이러한 요구사항들을 모두 만족할 수 없었다. 따라서 본 논문에서는 Failsafe 와 Blind Decoding 방법을 기본으로한 사용자와 정보의 요구사항을 모두 만족하는 새로운 키 위탁 시스템을 제안한다.

  • PDF

A FPGA Development for the Fail Safe Control of TMR System (TMR시스템의 고장안전제어를 위한 FPGA 개발)

  • 강민수;이정석;김현기;유광균;이기서
    • Proceedings of the KSR Conference
    • /
    • 2000.05a
    • /
    • pp.336-343
    • /
    • 2000
  • This paper proposes the failsafe control logic. which has applied to the voting on the TMR system by using FPGA The self-detection circuit is also designed for detecting a characteristic of fault at TMR system. The fault producing in the self-detection system is largely classified among an intermittent fault, a transient fault and a permanent fault. If it is happened to the permanent fault, the system can be failed. Therefore, it is designed the logic circuit which is not transferred the permanent fault to the system after shut off output. The control logic of the Fail Safe proposed in the paper is required for a circuit integrate of device to minimize the failure happened. Therefore, it makes to design FPGA with modeling of VHDL. The circuit of the Fail Safe of TMR system is able to apply to nuclear system, rail-way system, aerospace and aircraft system which is required for high reliability.

  • PDF

A Study on Design of the Trip Computer for ECC System Based on Dynamic Safety System

  • Kim, Seog-Nam;Seong, Poong-Hyun
    • Nuclear Engineering and Technology
    • /
    • v.32 no.4
    • /
    • pp.316-327
    • /
    • 2000
  • The Emergency Core Cooling System in current nuclear power plants typically has a considerable number of complex functions and largely cumbersome operator interfaces. Functions for initiation, switch-over between various phases of operation, interlocks, monitoring, and alarming are usually performed by relays and analog comparator logic which are difficult to maintain and test. To improve problems of an analog based ECC (Emergency Core Cooling) System, the trip computer for ECCS based on Dynamic Safety System (DSS) is implemented. The DSS is a computer based reactor protection system that has fail-safe nature and performs a dynamic self-testing. The most important feature of the DSS is the introduction of test signal that send the system into a tripped state. The test signals are interleaved with the plant signals to produce an output which switches between a tripped and health state. The dynamic operation is a key feature of the failsafe design of the system. In this work, a possible implementation of the DSS using PLC is presented for a CANDU Reactor. ECC System of the CANDU Reactor is selected as the reference system.

  • PDF