• Journal of Korean Society of Industrial and Systems Engineering
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• v.35 no.1
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• pp.79-86
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• 2012

This study focuses on the problem of scheduling wafer lots of several recipe(operation condition) types in the photolithography workstation in a semiconductor wafer fabrication facility, and sequence-dependent recipe set up times may be required at the photolithography machines. In addition, a lot is able to be operated at a machine when the reticle(mask) corresponding to the recipe type is set up in the photolithography machine. We suggest various heuristic algorithms, in which developed recipe selection rules and lot selection rules are used to generate reasonable schedules to minimizing the total weighted flowtime. Results of computational tests on randomly generated test problems show that the suggested algorithms outperform a scheduling method used in a real manufacturing system in terms of the total weighted flowtime of the wafer lots with ready times.

• Journal of the Korea Society for Simulation
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• v.32 no.3
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• pp.67-74
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• 2023

A semiconductor fabrication facility(FAB) is one of the most capital-intensive and large-scale manufacturing systems which operate under complex and uncertain constraints through hundreds of fabrication steps. To improve fab performance with intuitive scheduling, practitioners have used weighted-sum scheduling. Since the determination of weights in the scheduling significantly affects fab performance, they often rely on simulation-based decision making for obtaining optimal weights. However, a large-scale and high-fidelity simulation generally is time-intensive to evaluate with an exhaustive search. In this study, we investigated three sampling methods (i.e., Optimal latin hypercube sampling(OLHS), Genetic algorithm(GA), and Decision tree based sequential search(DSS)) for the optimization. Our simulation experiments demonstrate that: (1) three methods outperform greedy heuristics in performance metrics; (2) GA and DSS can be promising tools to accelerate the decision-making process.

• Korean Management Science Review
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• v.32 no.4
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• pp.69-80
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• 2015

The semiconductor industry is one of those in which the most intricate processes are involved and there are many critical factors that are controlled with precision in those processes. Naturally production scheduling in the semiconductor industry is also very complex and studied by the industry and academia for many years; however, still there are many issues left unclear in the problem. This paper proposes an multi-objective optimization-based scheduling method for semiconductor fabrication(fab). Two main objectives are throughput maximization and meeting target production quantities. The first objective aims to reduce production cost, especially the fixed cost incurred by a large investment constructing a new fab facility. The other is meeting customer orders on time and also helps a fab maintain stable throughput through controlled WIP balancing in the long run. The paper shows a trade-off structure between the two objectives through experimental studies, which provides industrial practitioners with useful references.

• Journal of the Korea Society for Simulation
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• v.8 no.3
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• pp.49-66
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• 1999

Semiconductor wafer fabrication is known to be one of the most complex manufacturing processes due to process intricacy, random yields, product diversity, and rapid changing technologies. In this study we are concerned with the impact of lot release and dispatching policies on the performance of semiconductor wafer fabrication facilities. We consider several semiconductor wafer fabrication environments according to the machine failure types such as no failure, normal MTBF, bottleneck with low MTBF, high randomness, and high MTBF cases. Lot release rules to be considered are Deterministic, Poisson process, WR(Workload Regulation), SA(Starvation Avoidance), and Multi-SA. These rules are combined with several dispatching rules such as FIFO (First In First Out), SRPT (Shortest Remaining Processing Time), and NING/M(smallest Number In Next Queue per Machine). We applied the combined policies to each of semiconductor wafer fabrication environments. These policies are assessed in terms of throughput and flow time. Basically Weins fabrication setup was used to make the simulation models. The simulation parameters were obtained through the preliminary simulation experiments. The key results throughout the simulation experiments is that Multi-SA and SA are the most robust rules, which give mostly good performance for any wafer fabrication environments when used with any dispatching rules. The more important result is that for each of wafer fabrication environments there exist the best and worst choices of lot release and dispatching policies. For example, the Poisson release rule results in the least throughput and largest flow time without regard to failure types and dispatching rules.

• Journal of the Korea Society for Simulation
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• v.9 no.3
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• pp.13-26
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• 2000

The scheduling rule for the fabrication process of the semiconductor manufacturing is suggested and tested on the simulation system which was developed based on the model to represent the main characteristics of wafer flows. The proper scheduling policies are necessary to meet the order change in the supply chain management. It was shown that the suggested rules which consider the wafer balance and the due date of the order, give good performances for the cycle time reduction and the rate of meeting due date as well. Also they are robust in the sense that performances are stable regardless of the order change rate and the input policies.

• Journal of the Society of Naval Architects of Korea
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• v.41 no.5
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• pp.55-62
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• 2004

The logistics of entire shipbuilding process are integrated during the block erection process and the schedules for the erection process are made prior to. the schedules of any other processes. Therefore, efficient scheduling of the block erection process are one of most important issues in shipbuilding. There are only a few studies published regarding block erection scheduling methods because of its complexity and variability. This paper proposes an algorithm for diminution of maximum load based on constraint satisfaction technique. it is developed primarily for the efficiency in load leveling and applicability to the actual block erection process. The proposed algorithm is applied to actual block erection process and the results shows improvements in load leveling. It can also be used for the scheduling of fabrication, sub-assembly, and assembly to improve load leveling.

• Journal of Korean Institute of Industrial Engineers
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• v.28 no.4
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• pp.415-424
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• 2002

Semiconductor manufacturing has been emerged as a highly competitive but profitable business. Accordingly it becomes very important for semiconductor manufacturing companies to meet customer demands at the right time, in order to keep the leading edge in the world market. However, due-date oriented production is very difficult task because of the complex job flows with highly resource conflicts in fabrication shop called FAB. Due to its cyclic manufacturing feature of products, to be completed, a semiconductor product is processed repeatedly as many times as the number of the product manufacturing cycles in FAB, and FAB processes of individual manufacturing cycles are composed with similar but not identical unit processes. In this paper, we propose a production scheduling and control scheme that is designed specifically for semiconductor scheduling environment (FAB). The proposed scheme consists of three modules: simulation module, cycle due-date estimation module, and dispatching module. The fundamental idea of the scheduler is to introduce the due-date for each cycle of job, with which the complex job flows in FAB can be controlled through a simple scheduling rule such as the minimum slack rule, such that the customer due-dates are maximally satisfied. Through detailed simulation, the performance of a cycle due-date based scheduler has been verified.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2007.05a
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• pp.368-370
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• 2007

AAO(Anodic Aluminum Oxidation) method has been known that it is practically useful for the fabrication of nano-structures and makes it possible to fabricate the highly ordered nano masters on large surface and even on the 2.5 or 3D surface at low cost comparing to the expensive e-beam lithography or the conventional silicon processing. In this study, by using the multi-step anodizing and etching processes, highly ordered nano patterned master with concave shapes was fabricated. By varying the processing parameters, such as initial matter and chemical conditions; electrical and thermal conditions; time scheduling; and so on, the size and the pitch of the nano pattern can be controlled. Consequently, various alumina/aluminum nano structures can be easily available in any size and shape by optimized anodic oxidation in various aqueous acids. The resulting good filled uniform nano molded structure through hot embossing molding process shows the validity of the fabricated nano pattern masters.

• Journal of the Society of Naval Architects of Korea
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• v.51 no.6
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• pp.510-520
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• 2014

Unlike other mass production in small variety, shipbuilding process is a project-based method in single variety, which causes unpredictable volatility in the planning system. In shipyards, series of manufacturing processes from fabrication to erection is sequentially carried out. In order to predict unfavorable changes such as overload or low load of working volume, computerized simulation has been being gradually adopted. The data used in the simulation are processed from the database of the main scheduling and planning system. Thus the quality of those data is very crucial for the meaningful results. Unfortunately, research on the verification of data quality is very rare and hardly known to the authors. In this work, using the database of scheduling and product information system of a large domestic shipyard, the data required for the simulation are qualitatively analyzed and verified.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1991.10a
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• pp.67-76
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• 1991

For several years, graduate students and faculty of the Engineering Systems Research Center at U.C., Berkeley have been studying new methods of planning and scheduling in a computer integrated manufacturing environment, with particular emphasis on large scale integrated circuit fabrication. One part of this work, focusing on short interval scheduling, uses simulation models as a primary research tool. We have built two versions of the same basic model (programmed in C) to study two different problems (one deals with machine down time and the other with setup times). These have proven to be efficient for studying particular problems, but are difficult and time consuming to modify. We are convinced that our research will be more effective: (1) if it were easier to build special purpose models tailored to the research question at hand; and (2) if we had better interfaces to graphics output. Commercially available factory simulators are inadequate for this research for a variety of reasons. Existing packages such as SIMKIT, SLAM, SIMAN and EXCELL have their own weaknesses. Typically, they are hard to develop and to modify. They do not allow for adding new dispatching decisions or release decision. Also, it is hard to add more machines to existing environment or change the route the product flows. For these various reasons, we had developed a new simulation package having flexibility and modularity. In this paper, based on experiences gained in the application of object oriented programming, we discuss unique features of the simulator developed in OOPS and ways to take advantage of features in developing and using manufacturing simulation software written in the OOPS