• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.34-42
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• 2012

In this paper, a wide-input range CMOS multi-mode rectifier for wireless power transfer system is presented. The output voltage of multi-mode rectifier is sensed by comparator and switches are controlled based on it. The mode of multi-mode rectifier is automatically selected by the switches among full-wave rectifier, 1-stage voltage multiplier and 2-stage voltage multiplier. In full-wave rectifier mode, the rectified output DC voltage ranges from 9 V to 19 V for a input AC voltage from 10 V to 20 V. However, the input-range of the multi-mode rectifier is more improved than that of the conventional full-wave rectifier by 5V, so the rectified output DC voltage ranges from 7.5 V to 19 V for a input AC voltage from 5 V to 20 V. The power conversion efficiency of the multi-mode rectifier is 94 % in full-wave rectifier mode. The proposed multi-mode rectifier is fabricated in a $0.35{\mu}m$ CMOS process with an active area of $2500{\mu}m{\times}1750{\mu}m$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.18-27
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• 2010

In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage，due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.35-40
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• 2010

In this paper, we propose a hardware resource sharable camera control processor (CCP) for low-cost and low-power camera cell phones. The main idea behind the proposed architecture is that adds direct access paths in the CCP to share its hardware resources so that the baseband processor expands its capabilities and boosts its performance by utilizing CCF's hardware resources. In addition, we applied a module grain dock-gating method to reduce power dissipation. Hence, the CCP can realize low-power and low-cost camera cell phones with greater hardware efficiency. This chip was fabricated in a 0.18um CMOS process with an active area of $3.8mm\;{\times}\;3.8mm$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.58-64
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• 2008

A 6Gbps 1:2 demultiplexer(DEMUX) IC using $0.18{\mu}m$ CMOS was designed and fabricated. For high speed performance current mode logic(CML) flipflop was used and inductive peaking technology was used so as to obtain higher speed than conventional Current mode logic flipflop. On-chip spiral inductor was designed to maximize the inductive peaking effect using stack structure. Total twelve inductors of $100{\mu}m^2$ area increase was used. The measurement was processed on wafer and 1:2 demultiplexer with and without micro stacked spiral inductors were compared. For 6Gbps data rate measurement, eye width was improved 7.27% and Jitter was improved 43% respectively. Power consumption was 76.8mW and eye height was 180mV at 6 Gbps

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.11
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• pp.1121-1129
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• 2009

In this paper, the UWB(Ultra-Wide Band) modules such as a pulse generator and the LNA(Low-Noise Amplifier) with AGC(Auto Gain Control) are designed to construct a cross-borehole pulse radar system, of which performance is compared with the existing system. The budget and specification of the radar system are determined by calculating the total path loss of the underground medium including an empty cavity. The pulse generator is fabricated to have the repeatation frequency 40 kHz, the pulse width lower than 5 ns and the peak signal level +73 dBm. The UWB LNA is designed to have the noise figure 3.77 dB, the variable gain range 100 dB and the frequency range of 20 MHz to 200 MHz. Compared with the existing system in an actual test site, the implemented system renders it possible to detect the blind area due to the UWB LNA with low noise figure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5A
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• pp.504-512
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• 2010

The paper proposes the 6bit 800MS/s flash A/D converter that can be applied to wireless USB chip-set. The paper simplified the error correction circuit and synchronization block as one circuit which are used respectively, and furthermore reduced the burden on the hardware. Comparing to the conventional error correction circuit, the proposed error correction circuit in this paper reduced 5 MOS transistors, the area of each error correction circuit is reduced by 9%. The A/D converter is fabricated with 0.18um CMOS 1-poly 6-metal process, and power dissipation is 182mW at 0.8Vpp input range and 1.8V supply voltage. The measured result shows 4.0bit of ENOB at 800MS/s conversion rate and 128.1MHz input frequency.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.2
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• pp.146-153
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• 2008

Integrated humidity sensor system with two stages operational amplifier has been designed and fabricated by $0.8{\mu}m$ analog mixed CMOS technology. The system (28 pin and $2mm{\times}4mm$) consisted of Wheatstone-bridge type humidity sensor, resistive type humidity sensor, temperature sensors and operational amplifier for signal amplification and process in one chip. The poly-nitride etch stop process has been tried to form the sensing area as well as trench in a standard CMOS process. This modified technique did not affect the CMOS devices in their essential characteristics and gave an allowance to fabricate the system on same chip by standard process. The operational amplifier showed the stable operation so that unity gain bandwidth was more than 5.46 MHz and slew rate was more than 10 V/uS, respectively. The drain current of n-channel humidity sensitive field effect transistor (HUSFET) increased from 0.54 mA to 0.68 mA as the relative humidity increased from 10 to 70 %RH.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.36 no.12
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• pp.1497-1502
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• 2012

To manufacture a robot hand that essentially mimics the functions of a human hand, it is necessary to develop flexible actuators and sensors. In this study, we propose the design, manufacture, and performance verification of flexible actuators and sensors based on Electro Active Polymer (EAP). EAP is fabricated as a type of film, and it moves with changes in the voltage because of contraction and expansion in the polymer film. Furthermore, if a force is applied to an EAP film, its thickness and effective area change, and therefore, the capacitance also changes. By using this mechanism, we produce capacitive actuators and sensors. In this study, we propose an EAP-based capacitive sensor and evaluate its use as a robot hand sensor.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.2
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• pp.144-150
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• 1990

This paper describes radix-4 Fast Fourier Transform (FFT) Processor designed with the new twice perfect shuffle developed from a perfect shuffle used in radix-2 FFT algorithm. The FFT Processor consists of a butterfly arithmetic circuit, address generators for input, output and coefficient, input and output registers and controller. Also, it requires the external ROM for storage of coefficient and RAM for input and output. The butterfly circuit includes 12 bit-serial ($16{\times}8$) multipliers, adders, subtractors and delay shift registers. Operating on 25 MHz two phase clock, this processor can compute 256 point FFT in 6168 clocks, i.e. 247 us and provides flexibility by allowing the user to select any size among 4,16,64,and256points. Being fabricated with 2-um double metal CMOS process, it includes about 28000 transistors and 55 pads in $8.0{\times}8.2mm^2$area.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.532-541
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• 2003

In a memory, most power is dissipated in high capacitive lines such as predecoder lines, word lines, and bit lines. To reduce the power dissipation in these high capacitive lines, this paper proposes three techniques using charge recycling and charge sharing. One is the charge recycling predecoder (CRPD). The second one is the charge recycling word line decoder (CRWD). The last one is the charge sharing bit line (CSBL) for a ROM. The CRPD and the CRWD recycle the previously used charge in predecoder lines and word lines. Theoretically, the power consumption in predecoder lines and word lines are reduced to a half. The CSBL reduces the swing voltage in the ROM bit lines to very small voltage using a charge sharing technique. the CSBL can significantly reduce the power dissipation in ROM bit lines. The CRPD, the CRWD, and the CSBL consume 82%, 72%, and 64% of the power of previous ROM designs respectively. A charge recycling and charge sharing ROM (CRCS-ROM) with the CRPD, the CRWD, and the CSBL is implemented. A CRCS-ROM with 8K16bits was fabricated in a 0.3${\mu}{\textrm}{m}$ CMOS process. The CRCS-ROM consumes 8.63㎽ at 100MHz with 3.3V. The chip core area is 0.1 $\textrm{mm}^2$.