• ETRI Journal
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• v.10 no.3
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• pp.36-48
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• 1988

본 논문에서는 부동소숫점연산 프로세서들의 최근 동향을 설명하면서 부동소숫점 연산기의 중요성을 강조하고, 한국전자통신연구소 프로세서구조연구실에서 개발하고 있는 HARP(High-performance Architecture for RISC type Processor)의 개발전략에 따른 부동소숫점 연산기(Floating-Point Unit : FPU)의 구조를 정의한다. 또한 HARP FPU의 설계구현을 마이크로 구조측면에서 설명한다. HARP의 CPU와 동일 칩상에 구현될 HARP FPU는 고유의 구조를 가지며 모든 부동소숫점 연산은 IEEE-754 표준을 따른다. HARP FPU는 고속의 부동소숫점 연산 유니트이며, HARP의 IPU(Integer Processing Unit)와는 독립적으로 동작되도록 설계되어서 HARP CPU의 전체적인 파이프라인 기능에 가능한 한 페날티를 주지 않도록 동작된다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.4
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• pp.658-666
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• 2003

In this paper, we analyzed standard and characteristic of portable microwave digital FPU(Field Pick Up) transmission system in AWGN channel environment as basis step of research about share way of M/W broadcasting relay frequency. And we analyzed system performance through simulator design. Domestic case, digitize progress about broadcasting relay is propeled. Therefore, we wish to utilize to basis data about interference evaluation and domestic broadcasting relay standardization for reassignment of M/W band broadcasting relay frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4C
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• pp.388-397
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• 2002

We designed a SIMD-DSP/FPU that can efficiently improve multimedia processing performance when integrated into high-performance embedded microprocessors. We proposed partitioned architectures and new schemes for several functional units to reduce chip area. Sharing functional units reduces the area of FPU significantly. The proposed architecture is modeled in HDL and synthesized with a 0.35$\mu\textrm{m}$ standard cell library. The chip area is estimated to be about 100,000 equivalent gates. The designed unit can run at higher than 50MHz clock frequency of CPU core under the worst-case operating conditions.

• Journal of IKEEE
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• v.11 no.4
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• pp.358-363
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• 2007

This paper presents a floating point unit(FPU) with 3 stages for a 3D graphics shader engine. It targeted to accelerate 3D graphics in portable device environments. In order to design a balanced architecture for a shader engine, we analyzed shader assembly instructions and estimated the performance of FPU with the method we propose. The proposed unit handles 4-dimensional data through separated two paths that are lead to general operation module and special function module. The proposed FPU is compiled as a form of the cascade FPU with 3 stages to efficiently handle a matrix operation with relatively low hardware overhead. Except some complex instructions that are executed using macro instructions, all instructions complete an operation in a single instruction cycle at 100MHz frequency. A special function module performs all operations in a single clock cycle using the Newton Raphson method with the look-up table.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.123-126
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• 2004

현재 방송중계용으로 쓰이는 주파수대는 3~30GHz의 M/W 대역이다. 그러나 갈수록 늘어나는 서비스와 전송용량의 증대로 인해 주파수 부족현상이 일어나는 추세이다. 이에 대안 방안으로 주파수 재배치에 관하여 대두가 되고 있다. 이동방송 중계용 링크인 FPU 링크는 차후 다른 주파수 대역으로 이전시 이러한 링크에서 사용되었던 시스템 제원을 토대로 필요한 대역에 대한 다양한 변조방식으로 먼저 시뮬레이션 평가 후 이용채널 개수 및 이전 가능 여부 둥과 같은 조치가 수행되어져야 한다. 본 논문에서는 M/W대역의 주파수를 이용한 서비스 중의 하나인 이동전송용 중계방송시스템인 FPU(Field Pick Up)시스템을 구현하고 무선채널에서 영상을 전송하였을 때의 성능을 PSNR, BER의 특성을 통하여 평가하였다. 전송되는 데이터는 실제 동영상(320$\times$240 61frame)을 동영상 압축방식 중 하나인 MPEG을 이용하여 압축하고, 압축된 영상 정보를 무선 채널상에 전송하였을 때 복원된 영상을 분석하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.82-90
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• 2011

Because of the development of Smart phone devices, the demands of high performance FPU(Floating-point Unit) becomes increasing. Therefore, we propose the high-speed single-/double-precision FPU design that includes an elementary add/sub unit and improved multiplier and compare and convert units. The most commonly used add/sub unit is optimized by the parallel rounding unit. The matrix operation is used in complex calculation something like a graphic calculation. We designed the Multiply-Add Fused(MAF) instead of multiplier to calculate the matrix more quickly. The branch instruction that is decided by the compare operation is very frequently used in various programs. We bypassed the result of the compare operation before all the pipeline processes ended to decrease the total execution time. And we included additional convert operations that are added in IEEE754-2008 standard. To verify our RTL designs, we chose four hundred thousand test vectors by weighted random method and simulated each unit. The FPU that was synthesized by Samsung's 45-nm low-power process satisfied the 600-MHz operation frequency. And we confirm a reduction in area by comparing the improved FPU with the existing FPU.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.398-400
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• 1996

We present the implementation of the adaptive filter for EMG signal processing using VHDL. For making ASIC, the basic FPU(floating point processor), e.g., adder, multiplier and divider, are implemented with VHDL. The FPU is simulated and the controller for the RLSL(recursive least square lattice) algorithm of the adaptive filter is implemented. Then FPU and the controller are linked and simulated. Finally the models are synthesized and the gate level is implemented.

• International Journal of Naval Architecture and Ocean Engineering
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• v.8 no.5
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• pp.487-495
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• 2016

In the offshore project such as semi-submersible FPU and FPSO, the free fall type life boat called TEMPSC (Totally Enclosed Motor Propelled Survival Craft) has been installed for the use of an emergency evacuation of POB (People on Board) from the topside platform. For the design of life boat arrangement for semi-submersible FPU in the initial design stage, the drop height and launch angle are required fulfill with the limitation of classification society rule and Company requirement, including type of approval as applicable when intact and damage condition of the platform. In this paper, we have been performed the numerical studies to find proper arrangement for the life boats consider drop height in various environmental conditions such as wave, wind and current. In the calculations, the contributions from static and low frequency (LF) motions are considered from the hydrodynamic and mooring analysis as well as damage angle from the intact and damage stability analysis. Also, Air-gap calculation at the life boat positions has been carried out to check the effect on the life boat arrangement. The air-gap assessment is based on the extreme air-gap method includes the effect of 1st order wave frequency (WF) motions, 2nd order low frequency roll/pitch motion, static trim/heel and set down.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.886-889
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• 2006

수치연산 보조프로세서로도 알려져 있는 부동 소수점 연산장치(FPU)는 컴퓨터가 사용하는 기본 마이크로프로세서보다 더 빠르게 숫자를 다를 수 있는 특별한 회로 설계 또는 마이크로프로세서를 말한다. FPU는 전적으로 대형 수학적 연산에만 초점을 맞춘 특별한 명령 셋을 가지고 있어서 그렇게 빠르게 계산을 수행할 수 있는 것이다. FPU는 오늘날의 거의 모든 PC에 장착되고 있지만, 실은 그것은 그래픽 이미지 처리나 표현 등과 같은 특별할 일을 수행할 때에 필요하다. 초창기 컴퓨터 회사들은 각기 다른 연산방식을 사용했다. 이에 따라 연산결과가 컴퓨터마다 다른 문제점을 해결하기 위해 IEEE에서는 부동 소수점에 대한 표준안을 제안하였다. 이 표준안은 IEEE Standard 754 이며, 오늘날 인텔 CPU 기반의 PC, 매킨토시 및 대부분의 유닉스 플랫폼에서 컴퓨터 상의 실수를 표현하기 위해 사용하는 가장 일반적인 표현 방식으로 발전하였다. 본 논문에서는 부동 소수점 표준안 중 32-bit 단일 정밀도 부동 소수점 가산기를 VHDL로 구현하여 FPGA칩으로 다운하고 PCI 인터페이스를 통해 Visual C++로 데이터의 입출력을 검증하였다.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2861-2873
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• 1997

An FPU(Floating Point unit) is the principle component in high performance computer and is placed on a chip together with main processing unit recently. As a Processing speed of the FPU is accelerated, the rounding stage, which occupies one of the floating point Processing steps for floating point operations, has a considerable effect on overall floating point operations. In this paper, by studying and analyzing the processing flows of the conventional floating point adder/subtractor, multipler and divider, which are main component of the FPU, efficient rounding mechanisms are presented. Proposed mechanisms do not require any additional execution time and any high speed adder for rounding operation. Thus, performance improvement and cost-effective design can be achieved by this approach.