• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.118-125
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• 2016

This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.152.4-152
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• 2001

We investigate, in this paper, the use of FPGA(Field Programmable Gate Array) architectures for real-time processing of digital linescan camera. The use of FPGAS for low-level processing represents an excellent tradeoff between software and special purpose hardware implementations. A library of modules that implement common low-level machine vision operations is presented. These modules are designed with gate-level hardware components that are compiled into the functionality of the FPGA chips. This new synchronous unidirectional interface establishes a protocol for the transfer of image and result data between modules. This reduces the design complexity and allows several different low-level operations to be applied to the same input image ...

• 대한전자공학회논문지SD
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• 제41권4호
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• pp.113-122
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• 2004

본 논문에서는 FPGA 연결선을 위한 고장 진단 방안을 제안한다. 제안된 고장 진단 방안은 FPGA의 연결선에 존재하는 모든 고장을 진단한다. 또한 이는 최신의 FPGA 장치인 Xilinx Virtex FPGA에 적용이 가능하다. 제안된 고장 진단 방안은 기존의 고장 진단 방안에 비하여 훨씬 짧은 시간동안 고장 진단을 수행한다.

• 전자공학회논문지A
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• 제31A권2호
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• pp.125-134
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• 1994

This paper proposes a new top-down technology mapping algorithm for minimizing the chip area and the path delay time of lookup table-based field programmable gate array(FPGA). First, we present the decomposition and factoring algorithm using common subexpre ssion which minimizes the number of basic logic blocks and levels instead of the number of literals. Secondly, we propose a cube packing algorithm considering the decomposition of gates which exceed m-input lookup table. Previous approaches perform the cube packing and the gate decomposition independently, and it causes to increase the number of basic logic blocks. Lastly, the efficiency.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2003년도 춘계 학술대회 학술발표 논문집
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• pp.299-302
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• 2003

대용량의 퍼지데이터를 처리하기 위한 퍼지제어 시스템의 가장 큰 과제는 퍼지추론 및 비퍼지화 단계에서의 수행속도의 개선이다. 본 논문에서는 퍼지제어기의 속도 향상을 위해 [0, 1]사이의 실수값을 갖는 퍼지 소속 함수값을 정수형 격자(pixel)에 매핑시켜 정수형 퍼지 소속함수값만을 가지고 퍼지연산을 하는 정수형 퍼지제어기법을 적용한 고속이 정수 연산을 수행하는 퍼지 프로세서와 주변제어 시스템을 FPGA로 설계하여 기존 퍼지제어 시스템에 비해 매우 빠른 실시간 고속퍼지 제어시스템을 구현한다.

• 한국컴퓨터정보학회논문지
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• 제22권7호
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• pp.9-16
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• 2017

In this paper, we propose a development method of portable Automatic Test Equipment based on PXIe platform. Legacy VME form factor structured test equipment has limited reuse and expansion of modules due to unapplied bus specification. In particular, these limitations can cause development periods and costs to increase, and the reliability of environmental conditions is lacking due to non-standard modules. The test equipment of the proposed PXIe platform can use diverse COTS modules to shorten the development period and minimize the instability between developments. The PXIe development module works with standard Xilinx FPGAs, PXIe Windows device drivers, and applications on standard PXIe buses. The use of standard bus and COTS modules increases scalability and reusability, enabling rapid development and excellent maintenance. Through the test, we show the proposed test equipments can be implemented efficiently between the development processes and proved their reliability through function tests and environmental tests.

• 디지털산업정보학회논문지
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• 제9권1호
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• pp.111-118
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• 2013

This paper presents implementation of Air protocol analyzer and physical layer design algorithm. The analyzer is a measurement system providing real-time analysis of wireless signals between User Equipment (UE) and Node-B. The implemented system proposed in this paper consists of Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The waveform of Wideband Code Division Multiple Access (WCDMA) has been selected for verification of the proposed system. We designed the analyzer using equalizer algorithm and rake-receiver algorithm. Among various algorithms of designing the equalizer, we have chosen Linear Minimum Mean Square Error (LMMSE) equalizer that uses the inverse of channel matrix. Since the LMMSE equalizer uses the inverse channel matrix, it suffers from a large amount of computational load, while it outperforms most conventional equalizers. In this paper, we introduce an efficient procedure of reducing the computational load required by LMMSE equalizer-based receiver.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1428-1431
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• 2002

It is general opinion that the future mobile multimedia networks will use different standards and a prospective solution to this problem will be software defined radio (SDR) techniques. SDR provides the flexibility to support multiple air interfaces and signal processing functions at the same time. Especially, digital signal processors and FPGAs are widely used for implementation of these adaptive and flexible functions of a baseband modem for SDR applications. Also, it is known that the modulation schemes of OCQPSK (Orthogonal Complex QPSK) and HPSK (Hybrid PSK) are used for IMT-2000 services of cdma2000 and WCDMA, respectively. Thus, in this paper, we design and implement an OCQPSK / HPSK modem using a DSP chip of Texas Instrument's TMS320C6701. One modulation scheme is operated by adaptive selection between the two schemes and 5 physical traffic channels differentiated by orthogonal codes are implemented in one DSP chip and each channel has 1Mbps data rates and 8Mcps chip rates.

• 전자공학회논문지C
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• 제34C권2호
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• pp.38-49
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• 1997

In this paper, w describe partitioning large circuits into multiple chips on the programmable FPCB for rapid prototyping. FPCBs consists of areas for FPGAs for logic and interconnect components, and the routing topology among them are predetermined. In the partition problem for FPCBs, the number of wires ofr routing among chips is fixed, which is an additonal constraints to the conventional partition problem. In order to deal with such aconstraint properly we first define a new partition problem, so called the topologybased partition problem, and then propose a heuristic method. The heuristic method is based on the simulated annealing and clustering technique. The multi-level tree clustering technique is used to obtain faster and better prtition results. In the experimental results for several test circuits, the restrictions for FPCB were all satisfied and the needed execution time was about twice the modified K-way partition method for large circuits.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 1999년도 추계종합학술대회
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• pp.534-537
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• 1999

This paper describes a design of pipelined adaptive decision-feedback equalizer (PADFE) for high bit-rate wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of ADFE by using delayed least-mean-square (DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of ADFE including filter laps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters (filter tap, coefficient and internal bit-width, etc.) and equalization performance (bit error rate, convergence speed, etc.) are analyzed by algorithm-level simulation using COSSAP. The PADFE was designed using VHDL and Synopsys, and mapped into two ALTERA FLEX10k100 FPGAs.